Digital logic simulation at the gate and functional level

• Authors: Phil Wilcox
• Venue: DAC '79 Proceedings of the 16th Design Automation Conference
• Year: 1979

Simulation, in several forms, is used extensively in present day circuit design. The various forms of simulation can be categorized in terms of level of detail offered, ranging from circuit level (transistors, capacitors, etc.) to timing level (e.g., MOTIS (1)) to logic gate level (NAND, NOR, etc.) to register transfer level. As with a microscope, increasing the resolution decreases the field of view. This 'law' imposes a constraint on the size of circuit a designer can simulate at any one level of detail, and most simulation programs are rigidly defined to operate at only one level. This leads to obvious problems, for example, when a circuit is mixed analog/digital, although some progress has been made on incorporating circuit level and gate level detail in one program(2). However, digital circuit sizes keep increasing and even now the gate level often offers too much resolution. To keep simulation costs down and to avoid overwhelming the macroscopic features of a circuit with irrelevant data another level of digital logic simulation is required. The various Hardware Description Languages(3) are too far removed from the gate level to be of much use here as they represent a very large, discrete jump from the gate level, when we would prefer a continuum of simulation resolution.