Event manipulation for discrete simulations requiring large numbers of events
Communications of the ACM
Exclusive simulation of activity in digital networks
Communications of the ACM
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
Table lookup techniques for fast and flexible digital logic simulation
DAC '80 Proceedings of the 17th Design Automation Conference
Fault-test analysis techniques based on logic simulation
DAC '72 Proceedings of the 9th Design Automation Workshop
Concurrent fault simulation and functional level modeling
DAC '77 Proceedings of the 14th Design Automation Conference
Digital logic simulation at the gate and functional level
DAC '79 Proceedings of the 16th Design Automation Conference
Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A new two task algorithm for clock mode fault simulation in sequential circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The architecture of a highly integrated simulation system
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
High level hierarchical fault simulation techniques
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
A design verification methodology based on concurrent simulation and clock suppression
DAC '83 Proceedings of the 20th Design Automation Conference
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Diagnostic system for large scale logic cards and LSI'S.
DAC '81 Proceedings of the 18th Design Automation Conference
A MOS/LSI oriented logic simulator
DAC '81 Proceedings of the 18th Design Automation Conference
Table lookup techniques for fast and flexible digital logic simulation
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Speed and accuracy in digital network simulation based on structural modeling
DAC '82 Proceedings of the 19th Design Automation Conference
Computer-aided design of electrical circuits Simulation techniques (A Tutorial)
ACM '81 Proceedings of the ACM '81 conference
Evaluation of a fan out stem based fault simulation in sequential circuits
Mathematical and Computer Modelling: An International Journal
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Basic goals for logic and fault simulation are accuracy, execution speed, and modeling ease. Accuracy means that adequate state and timing detail must be maintained, and that good and faulted networks must be simulated with equal accuracy. High speed simulation is desirable to perform massive fault simulations of large networks, and modeling ease is desirable to build models easily and quickly. It should be observed that some of the above goals are in mutual conflict. For example, modeling ease and high execution speed are normally only achievable by a sacrifice in accuracy, and high accuracy is only possible by more elaborate modeling efforts or slower execution speeds, or both. As a consequence it becomes important to achieve a balance between these goals. The balance achieved here, in part dictated by the demands of fault simulation, emphasizes execution speed, adequate accuracy, and a simple modeling method. A new logic and fault simulator, VOTE (Verification of Test Effectiveness) is described. The specifics to be described here fall into two categories: those which are of general interest, and those which are strictly implementation items.