Exclusive simulation of activity in digital networks
Communications of the ACM
Theory and Design Switching Circ
Theory and Design Switching Circ
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Vector coding techniques for high speed digital simulation
DAC '81 Proceedings of the 18th Design Automation Conference
A parallel bit map processor architecture for DA algorithms
DAC '81 Proceedings of the 18th Design Automation Conference
High-speed concurrent fault simulation with vectors and scalars
DAC '80 Proceedings of the 17th Design Automation Conference
Table lookup techniques for fast and flexible digital logic simulation
DAC '80 Proceedings of the 17th Design Automation Conference
Design verification of large scientific computers
DAC '77 Proceedings of the 14th Design Automation Conference
HAL; A block level hardware logic simulator
25 years of DAC Papers on Twenty-five years of electronic design automation
Use of embedded scheduling to compile VHDL for effective parallel simulation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Modeling switch-level simulation using data flow
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Tutorial on parallel processing for design automation applications (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
HAL: A block level HArdware Logic simulator
DAC '83 Proceedings of the 20th Design Automation Conference
Functional models for VLSI design
DAC '83 Proceedings of the 20th Design Automation Conference
A design verification methodology based on concurrent simulation and clock suppression
DAC '83 Proceedings of the 20th Design Automation Conference
A systolic design rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
Parallel processing, special-purpose hardware, and DA applications
CSC-83 Proceedings of the 1983 computer science conference
Methodology for & results from the use of a hardware logic simulation engine for fault simulation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation machine employing distributed and parallel processing. Our architecture can accommodate different levels of modeling ranging from simple gates to complex functions, and support timing analysis. We estimate that simulation implemented by the proposed special-purpose hardware will be between 10 and 60 times faster than currently used software algorithms running on general-purpose computers. With the available technology, a throughput of 1,000,000 gate evaluations/second can be achieved.