The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
High-speed concurrent fault simulation with vectors and scalars
DAC '80 Proceedings of the 17th Design Automation Conference
Table lookup techniques for fast and flexible digital logic simulation
DAC '80 Proceedings of the 17th Design Automation Conference
Concurrent fault simulation and functional level modeling
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Speed and accuracy in digital network simulation based on structural modeling
DAC '82 Proceedings of the 19th Design Automation Conference
Automatic clock abstraction from sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Processor self-scheduling in parallel discrete event simulation
WSC '95 Proceedings of the 27th conference on Winter simulation
Algorithm for vectorizing logic simulation and evaluation of “VELVET” performance
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Optimizing VHDL Compilation for Parallel Simulation
IEEE Design & Test
Periodic signal suppression in a concurrent fault simulator
EURO-DAC '91 Proceedings of the conference on European design automation
Methodology for & results from the use of a hardware logic simulation engine for fault simulation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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This Paper outlines a methodology for design verification of very large networks based on Concurrent Simulation and Clock Suppression. Concurrent Simulation is expected to yield a 30:1 to 600:1 speed advantage over conventional (serial) simulation when roughly 5,000 “good machines” are simulated concurrently. This speed advantage increases with the number of concurrent machines. Clock Suppression is an auxiliary technique to avoid simulation slowdowns if very large networks with very large clock fanouts must be simulated. The methodology proposed here for design verification is “Concurrent Case Simulation”, i.e., the simultaneous simulation of distinct sets of input patterns. Advantages of this method are (1) speed, (2) the fundamental ability to simulate cases concurrently, (3) to observe differences between cases in a more economic, simpler, and more natural style than with serial simulation, (4) to run many more cases than would be possible with serial simulation, (5) and the fact that running cases against each other establishes a powerful design verification philosophy.