Event manipulation for discrete simulations requiring large numbers of events
Communications of the ACM
Exclusive simulation of activity in digital networks
Communications of the ACM
High-speed concurrent fault simulation with vectors and scalars
DAC '80 Proceedings of the 17th Design Automation Conference
Fault-test analysis techniques based on logic simulation
DAC '72 Proceedings of the 9th Design Automation Workshop
Time flow mechanisms for use in digital logic simulation
WSC '71 Proceedings of the 5th conference on Winter simulation
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Processor self-scheduling in parallel discrete event simulation
WSC '95 Proceedings of the 27th conference on Winter simulation
Modeling switch-level simulation using data flow
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A design verification methodology based on concurrent simulation and clock suppression
DAC '83 Proceedings of the 20th Design Automation Conference
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
High-speed concurrent fault simulation with vectors and scalars
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Speed and accuracy in digital network simulation based on structural modeling
DAC '82 Proceedings of the 19th Design Automation Conference
EURO-DAC '91 Proceedings of the conference on European design automation
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A well-known fundamental computer technique consists of the “interpretation” of naturally available or artifically formed data items as addresses to perform table-lookups. Although well-known, this technique is still not exploited to its fullest potential. The power and extent of this technique as applied to logic simulation is demonstrated.