First version of a data flow procedure language
Programming Symposium, Proceedings Colloque sur la Programmation
Vector coding techniques for high speed digital simulation
DAC '81 Proceedings of the 18th Design Automation Conference
MOSSIM: A switch-level simulator for MOS LSI
DAC '81 Proceedings of the 18th Design Automation Conference
Table lookup techniques for fast and flexible digital logic simulation
DAC '80 Proceedings of the 17th Design Automation Conference
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Hardware logic simulation by compilation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
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The complexity of simulating large circuits is a bottleneck in the design process. Considerable attention is being focused on using multiprocessing architectures to speed up simulation. In order to utilize these architectures one first needs to capture the parallelism inherent in the simulation process. This paper explores data flow graphs as a means of expressing the parallelism in switch-level simulation. These data flow graphs, when executed on general purpose or special purpose data flow machines should result in considerable speed up.