Introduction to VLSI Systems
IEEE Transactions on Computers
A hardware switch level simulator for large MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A rule-based circuit representation for automated CMOS design and verification
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A fault simulator for MOS LSI circuits
25 years of DAC Papers on Twenty-five years of electronic design automation
IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Extracting schematic-like information from CMOS circuit net-lists
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A new efficient approach to statistical delay modeling of CMOS digital combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
CMOS dynamic power estimation based on collapsible current source transistor modeling
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Event driven adaptively controlled explicit simulation of integrated circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
LOGEX—an automatic logic extractor form transistor to gate level for CMOS technology
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A case against event-driven simulation for digital system design
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Modeling switch-level simulation using data flow
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A workstation-mixed model circuit simulator
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
HISDL—a structure description language
Communications of the ACM
Programming aspects of VLSI: (preliminary version)
POPL '82 Proceedings of the 9th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Aquarius: Logic simulation on an Engineering Workstation
DAC '83 Proceedings of the 20th Design Automation Conference
Simulating pass transistor circuits using logic simulation machines
DAC '83 Proceedings of the 20th Design Automation Conference
A data structure for MOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
An experimental MOS fault simulation program CSASIM
DAC '84 Proceedings of the 21st Design Automation Conference
Functional verification of memory circuits from mask artwork data
DAC '84 Proceedings of the 21st Design Automation Conference
Oracle - a simulator for Bipolar and MOS IC design
DAC '84 Proceedings of the 21st Design Automation Conference
A fault simulator for MOS LSI circuits
DAC '82 Proceedings of the 19th Design Automation Conference
Programs for verifying circuit connectivity of mos/lsi mask artwork
DAC '82 Proceedings of the 19th Design Automation Conference
Parallel processing, special-purpose hardware, and DA applications
CSC-83 Proceedings of the 1983 computer science conference
VLSI tools and architectures: Putting the new technology to work
CSC-83 Proceedings of the 1983 computer science conference
Path runner: an accurate and fast timing analyser
EURO-DAC '90 Proceedings of the conference on European design automation
Parallel switch-level simulation for VLSI
EURO-DAC '91 Proceedings of the conference on European design automation
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
| Hi-index | 0.02 |
The logic simulator MOSSIM is designed specifically to serve the needs of the MOS LSI designer. It models a MOS circuit as a network of field-effect transistor “switches”, with node states 0, 1, and X (unknown) and transistor states “open”, “closed”, and “unknown”. MOSSIM has proved quite versatile and accurate in simulating a variety of MOS designs including ones for which the network was extracted automatically from the mask specifications. Because it models the network at a logical level, it has a performance comparable to conventional logic gate simulators.