MOSSIM: A switch-level simulator for MOS LSI
DAC '81 Proceedings of the 18th Design Automation Conference
DESB, a functional abstractor for CMOS VLSI circuits
EURO-DAC '92 Proceedings of the conference on European design automation
SubGemini: identifying subcircuits using a fast subgraph isomorphism algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Transistor reordering for low power CMOS gates using an SP-BDD representation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Efficient partitioning and analysis of digital CMOS-circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Candidate subcircuits for functional module identification in logic circuits
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
An Efficient Algorithm for Signal Flow Determination in Digital CMOS VLSI
EDTC '96 Proceedings of the 1996 European conference on Design and Test
SUBGEN: a genetic approach for subcircuit extraction
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Functional abstraction of logic gates for switch-level simulation
EURO-DAC '91 Proceedings of the conference on European design automation
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Transistor abstraction for the functional verification of FPGAs
Proceedings of the 43rd annual Design Automation Conference
External memory layout vs. schematic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Extraction error modeling and automated model debugging in high-performance custom designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Securing netlist-level FPGA design through exploiting process variation and degradation
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
| Hi-index | 0.00 |
A program for automatic extraction of a gate level description from a transistor level description based on the layout of a CMOS VLSI circuit is presented. The extraction algorithm combines transistors to gates of arbitrary complexity without the help of any cell library. The resulting gate level description provides the input for a digital logic simulator for further investigations.