Extraction error modeling and automated model debugging in high-performance custom designs

Authors:
Yu-Shen Yang;Andreas Veneris;Paul Thadikaran;Srikanth Venkataraman
Affiliations:
Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada;Department of Electrical and Computer Engineering and the Department of Computer Science, University of Toronto, Toronto, Canada;Intel Corporation, Hillsboro, OR;srikanth.venkataraman@intel.com
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Abstract

In the design cycle of high-performance integrated circuits, it is common that certain components are designed directly at the transistor level. This level of design representation may not be appropriate for test generation tools that usually require a model expressed at the gate level. Logic extraction is a key step in test model generation to produce a gate-level netlist from the transistor-level representation. This is a semi-automated process which is error-prone. Once a test model is found to be erroneous, manual debugging is required, which is a resourceintensive and time-consuming process. This paper presents an in-depth analysis of typical sets of extraction errors found in the test model representations of the pipelines in high-performance designs today. It also develops an automated debugging solution for single extraction errors for pipelines with no state equivalence information. A suite of experiments on circuits with similar architecture to that found in the industry confirms the fitness and practicality of the solution.