COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Simulating pass transistor circuits using logic simulation machines
DAC '83 Proceedings of the 20th Design Automation Conference
Functional abstraction of logic gates for switch-level simulation
EURO-DAC '91 Proceedings of the conference on European design automation
Candidate subcircuits for functional module identification in logic circuits
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
On Efficiently Producing Quality Tests forCustom Circuits in PowerPC™ Microprocessors
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Automated equivalence checking of switch level circuits
Proceedings of the 39th annual Design Automation Conference
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
MODELING AND TESTING THE GEKKO MICROPROCESSOR, AN IBM POWERPC DERIVATIVE FOR NINTENDO
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Critical Path Identification and Delay Tests of Dynamic Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design-For-Test Methodology for Motorola PowerPCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Tradeoff Analysis For Producing High Quality Tests For Custom Circuits in PowerPCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Modeling Custom Digital Circuits for Test
Journal of Electronic Testing: Theory and Applications
An automated method for test model generation from switch level circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Custom circuit design as a driver of microprocessor performance
IBM Journal of Research and Development
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
Extraction error modeling and automated model debugging in high-performance custom designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
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Hierarchy is key to managing design complexity. A hierarchicaldesign system needs to maintain many views of the same designentity. Some of the examples might be physical view for placement,routing and extraction; transistor schematic view for circuit simulation,timing characterization and noise analysis; a gate level schematicview-for timing, verification, logic simulation, fault simulationand automatic test pattern generation (ATPG); a register transferlevel (RTL) view-for specification and high level simulation etc. Inorder to achieve highest system performance, multiple design iterationsare necessary, each iteration involving both forward and backwardpass through hierarchy, with manual changes at any level of thehierarchy. This poses an essential challenge of keeping all views ofsame design entity in sync. In this paper we describe an automatictool called GateMaker that has been developed to extract a gatelevel schematic model from a transistor level shematic model for thepurposes of logic simulation, fault simulation and automatic testpattern generation. This eliminates a manual process and offersmanifold advantages that will be discussed in this paper.