VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Algorithms for Switch Level Delay Fault Simulation
Proceedings of the IEEE International Test Conference
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design Methodology for a 1.0 GHz Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Circuit Design Techniques for a Gigahertz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
An Introduction to Switch-Level Modeling
IEEE Design & Test
A Survey of Switch-Level Algorithms
IEEE Design & Test
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
Full chip false timing path identification: applications to the PowerPCTM microprocessors
Proceedings of the conference on Design, automation and test in Europe
Identification of Crosstalk Switch Failures in Domino CMOS Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Switch-level Delay Test of Domino Logic Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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Dynamic circuit families are commonly used toachieve high operating speeds in recent microprocessordesigns. Because of their noise sensitivity, it is necessary to design dynamic circuits accurately to achieveperformance goals and avoid problems with noise. Although individual cells can be analyzed effectively, timing verification of the entire design is not easy becauseof the increased complexity. In this paper, we developa new approach to find critical paths and generate testvectors for delay test of large dynamic circuits, giveninformation on the path delays of the unit cells. Weintroduce the concept of "path gates" to represent thedischarge paths in a dynamic circuit, and have developed an extraction tool (PEAR) to construct the pathgates. The critical path analyzer (CRITIC) is used toidentify the critical paths and generate delay tests forthe integrated units. The technique has been successfully applied to industry circuits.