An efficient finite element method for submicron IC capacitance extraction
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Mixed-swing quadrail for low power dual-rail domino logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Dynamic noise analysis in precharge-evaluate circuits
Proceedings of the 37th Annual Design Automation Conference
Universal fault simulation using fault tuples
Proceedings of the 37th Annual Design Automation Conference
Robust Path Delay-Fault Testability on Dynamic CMOS Circuits
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Current Testing Viability in Dynamic CMOS Circuits
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Detecting resistive shorts for CMOS domino circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Universal Test Generation Using Fault Tuples
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Clock Switching: A New Design for Current Testability (DcT) Method for Dynamic Logic Circuits
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Critical Path Identification and Delay Tests of Dynamic Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Harmony: static noise analysis of deep submicron digital integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
False coupling interactions in static timing analysis
Proceedings of the 38th annual Design Automation Conference
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
Journal of Electronic Testing: Theory and Applications
ATPG for Noise-Induced Switch Failures in Domino Logic
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
| Hi-index | 0.00 |
Capacitative coupling will become a dominant problemdue to increased parasitic capacitance between adjacentwires and faster signal switching rates. The couplingproblem is more acute for domino logic circuits since anirreversible gate output transition can result. We presenta method to analyze domino circuits for susceptibility tocrosstalk failures from a layout-extracted netlist. Specifi-cally, sites in the circuit that may fail due to crosstalk areidentified. In addition, failure sites are partitioned intotwo categories (faults or design errors) based on theirlikelihood of occurrence in the context of manufacturingvariations. The method has been implemented and appliedto a dual-rail dominoWallace tree circuit with littleloss in accuracy, resulting in a 37X speedup over a fullanalysis using Hspice.