Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
A unified approach to the extraction of realistic multiple bridging and break faults
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
VHDL fault simulation for defect-oriented test and diagnosis of digital ICs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A novel algorithm to extract two-node bridges
Proceedings of the 37th Annual Design Automation Conference
Stay away from minimum design-rule values
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Inductive Contamination Analysis (ICA) with SRAM Application
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation
Proceedings of the IEEE International Test Conference on Test and Design Validity
An Accurate Bridging Fault Test Pattern Generator
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
On Accurate Modeling and Efficient Simulation of CMOS Opens
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Simulation Results of an Efficient Defect-Analysis Procedure
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test generation for crosstalk-induced faults: framework and computational results
ATS '00 Proceedings of the 9th Asian Test Symposium
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Fault characterization of standard cell libraries using inductive contamination
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A fault model for switch-level simulation of gate-to-drain shorts
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Identification of Crosstalk Switch Failures in Domino CMOS Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Analysis of Interconnect Crosstalk Defect Coverage of Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics
ISMVL '02 Proceedings of the 32nd International Symposium on Multiple-Valued Logic
A probabilistic fault model for analog faults
EURO-DAC '91 Proceedings of the conference on European design automation
Extraction and simulation of realistic CMOS faults using inductive fault analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An efficient CMOS bridging fault simulator: with SPICE accuracy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From Contamination to Defects, Faults and Yield Loss: Simulation and Applications
From Contamination to Defects, Faults and Yield Loss: Simulation and Applications
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This paper presents a new model for gate-to-channel GOS defects. The transistors used in digital cell library are usually designed with a minimum-size. This new model permits to handle minimal-length transistors allowing the simulation of GOS defects ...