Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Functional test generation for delay faults in combinational circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
SIGMA: a simulator for segment delay faults
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Timing analysis based on primitive path delay fault identification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Test generation for primitive path delay faults in combinational circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Deriving Logic Systems for Path Delay Test Generation
IEEE Transactions on Computers
On primitive fault test generation in non-scan sequential circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Functional test generation for delay faults in combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Redundant Path Delay Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
False-Path Removal Using Delay Fault Simulation
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Identifying Redundant Path Delay Faults in Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Primitive Path Delay Fault Identification
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
On Invalidation Mechanisms for Non-Robust Delay Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ENHANCED DELAY DEFECT COVERAGE WITH PATH-SEGMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
TESTING OF CRITICAL PATHS FOR DELAY FAULTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Switch-level Delay Test of Domino Logic Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Effective Path Selection for Delay Fault Testing of Sequential Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Delay Testing with Clock Control: An Alternative to Enhanced Scan
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
Journal of Electronic Testing: Theory and Applications
Robust Testability of Primitive Faults using Test Points
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Generalized Sensitization using Fault Tuples
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Non-Enumerative Path Delay Fault Diagnosis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A new classification of path-delay fault testability in terms of stuck-at faults
Journal of Computer Science and Technology
Implicit grading of multiple path delay faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The coupling model for function and delay faults
Journal of Electronic Testing: Theory and Applications
a fuzzy model for path delay fault detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.01 |
We address the problem of testing circuits for temporal correctness. A circuit is considered delay-verifiable if its timing correctness can be established by applying delay tests. It is shown that verifying the timing of a circuit may require tests which can detect the simultaneous presence of more than one path delay fault. We provide a general framework for examining delay-verifiability by introducing a special class of faults called primitive path delay faults. It is necessary and sufficient to test every fault in this class to ensure the temporal correctness of combinational circuits. Based on this result, we develop a synthesis procedure for combinational circuits that can be tested for correct timing. Experimental data show that such implementations usually require less area than completely delay testable implementations.Index Terms驴Testing for timing correctness, path-delay faults, delay-verification tests, primitive path-delay faults, synthesis for delay-verifiability.