Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A diagnosability metric for parametric path delay faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Timing analysis based on primitive path delay fault identification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Test generation for primitive path delay faults in combinational circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On primitive fault test generation in non-scan sequential circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
9.2 On Delay-Untestable Paths and Stuck-Fault Redundancy
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Design for Primitive Delay Fault Testability
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Robust Testability of Primitive Faults using Test Points
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A new classification of path-delay fault testability in terms of stuck-at faults
Journal of Computer Science and Technology
Exploring linear structures of critical path delay faults to reduce test efforts
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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We present a novel and efficient method to identify all primitive single and multi path delay faults (PDFs) in multi-level combinational circuits. Our method is the first one to successfully target the primitive PDF identification problem for multi-level circuits - previous research results in this area have been limited either to the identification of primitive PDFs only for 2-level circuits, or to the identification of only a subset of the complete set of paths which need not be tested for delay faults. Our primitive PDF identification procedure is based on determining which paths or sets of paths determine the signal stabilization time at the circuit outputs. We demonstrate the feasibility of the approach for mid-sized benchmark circuits.