Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Test generation for primitive path delay faults in combinational circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A unified approach for timing verification and delay fault testing
A unified approach for timing verification and delay fault testing
Identification and Test Generation for Primitive Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Primitive Path Delay Fault Identification
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Bounding Circuit Delay by Testing a Very Small Subset of Paths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical path selection for delay fault testing based upon a statistical timing model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay fault coverage, test set size, and performance trade-offs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target path can then be validated through simple calculation. Yet, no decomposition process is available to find paths that satisfy the above property. In this paper, given a set of target critical paths, we propose a two-stage method to find a set of robust-testable paths (with smaller number than the original set). The first stage constructs a necessary subset for critical robust paths, and the second stage identifies remaining functional sensitizable segments and their corresponding composing robust paths. The experiments show that a large percentage (several benchmarks close to 100%, 75% on average) of critical paths can be covered for most circuits. All paths and coverage are verified to match the best possible results. The data also indicate that the remaining hard-to-test (functional sensitizable) paths actually result from only a few tens of segments in the circuit (except for one circuit, s35932). DfT technique can then be applied to these uncovered segments for full testability with small overheads.