Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A global approach to circuit size reduction
Proceedings of the fifth MIT conference on Advanced research in VLSI
Proving circuit correctness using formal comparison between expected and extracted behaviour
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
The Complexity of Equivalence and Containment for Free Single Variable Program Schemes
Proceedings of the Fifth Colloquium on Automata, Languages and Programming
REPRESENTING BOOLEAN FUNCTIONS WITH IF-THEN-ELSE DAGs
REPRESENTING BOOLEAN FUNCTIONS WITH IF-THEN-ELSE DAGs
Implicit and incremental computation of primes and essential primes of Boolean functions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault test generation for scan/hold circuits using Boolean expressions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Accelerating switch-level simulation by function caching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Technology mapping for electrically programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Using BDDs to verify multipliers
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Breadth-first manipulation of SBDD of Boolean functions for vector processing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Exact evaluation of diagnostic test resolution
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A new model for improving symbolic product machine traversal
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Exact calculation of synchronization sequences based on binary decision diagrams
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Functional approaches to generating orderings for efficient symbolic representations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Inductive verification of iterative systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Cross-fertilizing FSM verification techniques and sequential diagnosis
EURO-DAC '92 Proceedings of the conference on European design automation
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
On computing the transitive closure of a state transition relation
DAC '93 Proceedings of the 30th international Design Automation Conference
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
High-level symbolic construction technique for high performance sequential synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
The Size of Reduced OBDD's and Optimal Read-Once Branching Programs for Almost all Boolean Functions
IEEE Transactions on Computers
Efficient breadth-first manipulation of binary decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
New techniques for efficient verification with implicitly conjoined BDDs
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
A fully implicit algorithm for exact state minimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Improving the accuracy of circuit activity measurement
DAC '94 Proceedings of the 31st annual Design Automation Conference
Computing binary decision diagrams for VHDL data types
EURO-DAC '94 Proceedings of the conference on European design automation
A method for finding good Ashenhurst decompositions and its application to FPGA synthesis
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Analysis of switch-level faults by symbolic simulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient OBDD-based boolean manipulation in CAD beyond current limits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Gate-level simulation of digital circuits using multi-valued Boolean algebras
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power estimation techniques for integrated circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Cost-free scan: a low-overhead scan path design methodology
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
From VHDL to efficient and first-time-right designs: a formal approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis by spectral translation using Boolean decision diagrams
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Engineering change in a non-deterministic FSM setting
DAC '96 Proceedings of the 33rd annual Design Automation Conference
High performance BDD package by exploiting memory hierarchy
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Implementation of an efficient parallel BDD package
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Efficient solution of systems of Boolean equations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Controller optimization for protocol intensive applications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Compilation of optimized OBDD-algorithms
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
MORE: an alternative implementation of BDD packages by multi-operand synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
The maximal VHDL subset with a cycle-level abstraction
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Hmap: a fast mapper for EPGAs using extended GBDD hash tables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A divide-and-conquer approach for asynchronous interface synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
On the Expressive Power of OKFDDs
Formal Methods in System Design
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Interleaving based variable ordering methods for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Breadth-first manipulation of very large binary-decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Representation and symbolic manipulation of linearly inductive Boolean functions
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A symbolic algorithm for maximum flow in 0-1 networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Boolean algebraic test generation using a distributed system
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Tri-state bus conflict checking method for ATPG using BDD
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Detection of symmetry of Boolean functions represented by ROBDDs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Parallel breadth-first BDD construction
PPOPP '97 Proceedings of the sixth ACM SIGPLAN symposium on Principles and practice of parallel programming
A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Linear sifting of decision diagrams
DAC '97 Proceedings of the 34th annual Design Automation Conference
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Solving Boolean Equations Using ROSOP Forms
IEEE Transactions on Computers
Fast exact minimization of BDDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
The design of a cache-friendly BDD library
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The General Product Machine: a New Model for Symbolic FSM Traversal
Formal Methods in System Design
The Theory of Zero-Suppressed BDDs and the Number of Knight‘s Tours
Formal Methods in System Design
Rectification method for lookup-table type FPGA's
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficient Boolean function matching
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Exact Minimization of Binary Decision Diagrams Using Implicit Techniques
IEEE Transactions on Computers
ATPG tools for delay faults at the functional level
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ordered Binary Decision Diagrams and Minimal Trellises
IEEE Transactions on Computers
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
A Hierarchical Test Generation Approach for Large Controllers
IEEE Transactions on Computers
Distance driven finite state machine traversal
Proceedings of the 37th Annual Design Automation Conference
BDS: a BDD-based logic optimization system
Proceedings of the 37th Annual Design Automation Conference
Efficient manipulation algorithms for linearly transformed BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Automatic Vector Generation Using Constraints and Biasing
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
A BDD-based satisfiability infrastructure using the unate recursive paradigm
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On the generation of multiplexer circuits for pass transistor logic
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Automatic abstraciton for worst-case analysis of discrete systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Efficient abstract interpretation using component-wise homomorphisms
Proceedings of the 2nd ACM SIGPLAN international conference on Principles and practice of declarative programming
Accurate and efficient predicate analysis with binary decision diagrams
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Streaming BDD manipulation for large-scale combinatorial problems
Proceedings of the conference on Design, automation and test in Europe
Binary decision diagram with minimum expected path length
Proceedings of the conference on Design, automation and test in Europe
Characterization-free behavioral power modeling
Proceedings of the conference on Design, automation and test in Europe
Efficient encoding schemes for symbolic analysis of petri nets
Proceedings of the conference on Design, automation and test in Europe
The multiple variable order problem for binary decision diagrams: theory and practical application
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Formal verification of pulse-mode asynchronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Low power optimization technique for BDD mapped circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'
IEEE Transactions on Computers
ATPG tools for delay faults at the functional level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing
Proceedings of the 2002 international symposium on Physical design
Technology mapping for high-performance static CMOS and pass transistor logic designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Consistency restoriation and explanations in dynamic CSPs----application to configuration
Artificial Intelligence
The nonapproximability of OBDD minimization
Information and Computation
Ordered binary decision diagrams as knowledge-bases
Artificial Intelligence
Clairvoyant: a synthesis system for production-based specification
Readings in hardware/software co-design
IEEE Transactions on Computers
Nonmonotonic reasoning: from complexity to algorithms
Annals of Mathematics and Artificial Intelligence
Toupie: The µ-calculus over Finite Domains as a Constraint Language
Journal of Automated Reasoning
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Limits of Using Signatures for Permutation Independent Boolean Comparison
Formal Methods in System Design
Another Look at LTL Model Checking
Formal Methods in System Design
Factored Edge-Valued Binary Decision Diagrams
Formal Methods in System Design
Arithmetic Boolean Expression Manipulator Using BDDs
Formal Methods in System Design
Algebric Decision Diagrams and Their Applications
Formal Methods in System Design
A Symbolic Algorithms for Maximum Flow in 0-1 Networks
Formal Methods in System Design
A Characterization of Binary Decision Diagrams
IEEE Transactions on Computers
Efficient Boolean Manipulation with OBDD's Can be Extended to FBDD's
IEEE Transactions on Computers
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Formal Verification Using Edge-Valued Binary Decision Diagrams
IEEE Transactions on Computers
Integration, the VLSI Journal
Verifying integrity of decision diagrams
Integration, the VLSI Journal
Minimization of word-level decision diagrams
Integration, the VLSI Journal
An open framework for data-flow analysis in Java: extended abstract
PPPJ '02/IRE '02 Proceedings of the inaugural conference on the Principles and Practice of programming, 2002 and Proceedings of the second workshop on Intermediate representation engineering for virtual machines, 2002
Translation among CNFs, characteristic models and ordered binary decision diagrams
Information Processing Letters
Boolean Constraints for Binding-Time Analysis
PADO '01 Proceedings of the Second Symposium on Programs as Data Objects
Faster and Symbolic CTMC Model Checking
PAPM-PROBMIV '01 Proceedings of the Joint International Workshop on Process Algebra and Probabilistic Methods, Performance Modeling and Verification
Advances in Model Representations
PAPM-PROBMIV '01 Proceedings of the Joint International Workshop on Process Algebra and Probabilistic Methods, Performance Modeling and Verification
ASIAN '00 Proceedings of the 6th Asian Computing Science Conference on Advances in Computing Science
Security Goals: Packet Trajectories and Strand Spaces
FOSAD '00 Revised versions of lectures given during the IFIP WG 1.7 International School on Foundations of Security Analysis and Design on Foundations of Security Analysis and Design: Tutorial Lectures
Ordered Binary Decision Diagrams as Knowledge-Bases
ISAAC '99 Proceedings of the 10th International Symposium on Algorithms and Computation
Reasoning with Ordered Binary Decision Diagrams
ISAAC '00 Proceedings of the 11th International Conference on Algorithms and Computation
Translation among CNFs, Characteristic Models and Ordered Binary Decision Diagrams
ISAAC '01 Proceedings of the 12th International Symposium on Algorithms and Computation
Using Decision Procedures with a Higher-Order Logic
TPHOLs '01 Proceedings of the 14th International Conference on Theorem Proving in Higher Order Logics
Implementation of Propositional Temporal Logics Using BDDs
TABLEAUX '98 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods
Formal Verification Methods for Industrial Hardware Design
SOFSEM '01 Proceedings of the 28th Conference on Current Trends in Theory and Practice of Informatics Piestany: Theory and Practice of Informatics
A New Class of Functions for Abstract Interpretation
SAS '99 Proceedings of the 6th International Symposium on Static Analysis
Verifying Integrity of Decision Diagrams
SAFECOMP '98 Proceedings of the 17th International Conference on Computer Safety, Reliability and Security
CL '00 Proceedings of the First International Conference on Computational Logic
Improvements in BDD-Based Reachability Analysis of Timed Automata
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
On-the-Fly Verification of Linear Temporal Logic
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume I - Volume I
Structural Methods to Improve the Symbolic Analysis of Petri Nets
Proceedings of the 20th International Conference on Application and Theory of Petri Nets
Stochastic Colored Petri Net Models for Rainbow Optical Networks
Application of Petri Nets to Communication Networks, Advances in Petri Nets
Symbolic Methods for the State Space Exploration of GSPN Models
TOOLS '02 Proceedings of the 12th International Conference on Computer Performance Evaluation, Modelling Techniques and Tools
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A New 3D 6-Subiteration Thinning Algorithm Based on P-Simple Points
DGCI '02 Proceedings of the 10th International Conference on Discrete Geometry for Computer Imagery
Automated verification using deduction, exploration, and abstraction
Programming methodology
Handbook of automated reasoning
High-level test evaluation of asynchronous circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Quasi-algebraic decompositions of switching functions
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
On applicability of symbolic techniques to larger scheduling problems
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Synthesis of multilevel fault-tolerant combinational circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A BDD-based frontend for retargetable compilers
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Using symbolic techniques to find the maximum clique in very large sparse graphs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Proving testing preorders for process algebra descriptions
EDTC '95 Proceedings of the 1995 European conference on Design and Test
How many decomposition types do we need? [decision diagrams]
EDTC '95 Proceedings of the 1995 European conference on Design and Test
VERIFUL: VERIfication using FUnctional Learning
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Fast and Efficient Construction of BDDs by Reordering Based Synthesis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hybrid symbolic-explicit techniques for the graph coloring problem
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A symbolic simulation approach in resolving signals' correlation
SS '96 Proceedings of the 29th Annual Simulation Symposium (SS '96)
A study of composition schemes for mixed apply/compose based construction of ROBDDs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Diagnosis of parametric path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On More Efficient Combinational ATPG Using Functional Learning
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Primitive Path Delay Fault Identification
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Exact Path Delay Grading with Fundamental BDD Operations
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Minimization of Ordered Pseudo Kronecker Decision Diagrams
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Weak, strong, and strong cyclic planning via symbolic model checking
Artificial Intelligence - special issue on planning with uncertainty and incomplete information
OBDD-Based Optimization of Input Probabilities for Weighted Random Pattern Generation
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
The semantics and execution of a synchronous block-diagram language
Science of Computer Programming
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
IEEE Transactions on Computers
A tutorial introduction to symbolic model checking
Logic for concurrency and synchronisation
Fast functional evaluation of candidate OBDD variable orderings
EURO-DAC '91 Proceedings of the conference on European design automation
A BDD-Based Algorithm for Analysis of Multistate Systems with Multistate Components
IEEE Transactions on Computers
Implicit GSPN reachability set generation using decision diagrams
Performance Evaluation - Dependable systems and networks-performance and dependability symposium (DSN-PDS) 2002: Selected papers
Low power ATPG for path delay faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Implicit pseudo boolean enumeration algorithms for input vector control
Proceedings of the 41st annual Design Automation Conference
A 3D 12-subiteration thinning algorithm based on P-simple points
Discrete Applied Mathematics - The 2001 international workshop on combinatorial image analysis (IWCIA 2001)
Minimization of the expected path length in BDDs based on local changes
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Combining ordered best-first search with branch and bound for exact BDD minimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Conformant planning via symbolic model checking and heuristic search
Artificial Intelligence
Efficient Relational Calculation for Software Analysis
IEEE Transactions on Software Engineering
Low power test generation for path delay faults using stability functions
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Integrating CNF and BDD based SAT solvers
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Mathematical framework for representing discrete functions as word-level polynomials
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
TED+: a data structure for microprocessor verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Lower bounds for dynamic BDD reordering
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Analysis and synthesis of quantum circuits by using quantum decision diagrams
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A 3D 6-subiteration curve thinning algorithm based on P-simple points
Discrete Applied Mathematics - Special issue: IWCIA 2003 - Ninth international workshop on combinatorial image analysis
Modeling and verifying behavioral aspects
Formal methods for embedded distributed systems
Strong planning under partial observability
Artificial Intelligence
Boolean equation solving as graph traversal
CATS '06 Proceedings of the 12th Computing: The Australasian Theroy Symposium - Volume 51
Improvements for constraint solving in the systemc verification library
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Verification method of dataflow algorithms in high-level synthesis
Journal of Systems and Software
A Technique for Estimating Signal Activity in Logic Circuits
Integrated Computer-Aided Engineering
Probabilistic decision diagrams for exact probabilistic analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
DySy: dynamic symbolic execution for invariant inference
Proceedings of the 30th international conference on Software engineering
On the construction of small fully testable circuits with low depth
Microprocessors & Microsystems
Redundancy-free residual dispatch: using ordered binary decision diagrams for efficient dispatch
Proceedings of the 7th workshop on Foundations of aspect-oriented languages
Shared Ordered Binary Decision Diagrams for Dempster-Shafer Theory
ECSQARU '07 Proceedings of the 9th European Conference on Symbolic and Quantitative Approaches to Reasoning with Uncertainty
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Efficient Term-ITE Conversion for Satisfiability Modulo Theories
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
Weighted A∗ search -- unifying view and application
Artificial Intelligence
A two-step hierarchical algorithm for model-based diagnosis
AAAI'06 Proceedings of the 21st national conference on Artificial intelligence - Volume 1
State agnostic planning graphs and the application to belief-space planning
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 3
Conformant planning via symbolic model checking
Journal of Artificial Intelligence Research
Planning graph heuristics for belief space search
Journal of Artificial Intelligence Research
Journal of Artificial Intelligence Research
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
Strong planning under partial observability
Artificial Intelligence
Computation of signal output probability for Boolean functions represented by OBDD
Computers & Mathematics with Applications
A 3D 6-subiteration curve thinning algorithm based on P-simple points
Discrete Applied Mathematics - Special issue: IWCIA 2003 - Ninth international workshop on combinatorial image analysis
Automated composition of Web services via planning in asynchronous domains
Artificial Intelligence
Computer Vision and Image Understanding
Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
Electronic Notes in Theoretical Computer Science (ENTCS)
Boolean approximation revisited
SARA'07 Proceedings of the 7th International conference on Abstraction, reformulation, and approximation
Dynamically resizable binary decision diagrams
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Pex: white box test generation for .NET
TAP'08 Proceedings of the 2nd international conference on Tests and proofs
Parallel disk-based computation for large, monolithic binary decision diagrams
Proceedings of the 4th International Workshop on Parallel and Symbolic Computation
Boolean affine approximation with binary decision diagrams
CATS '09 Proceedings of the Fifteenth Australasian Symposium on Computing: The Australasian Theory - Volume 94
Validating low-level instructions for fixnums using BDDs
Proceedings of the 2010 international conference on Lisp
A hybrid fault simulator for synchronous sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
Full symbolic ATPG for large circuits
ITC'94 Proceedings of the 1994 international conference on Test
Testing techniques in software engineering
Testing techniques in software engineering
Symbolic automata constraint solving
LPAR'10 Proceedings of the 17th international conference on Logic for programming, artificial intelligence, and reasoning
Improved diagnosis using enhanced fault dominance
Integration, the VLSI Journal
IDD-based model validation of biochemical networks
Theoretical Computer Science
Clairvoyant: a synthesis system for production-based specification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic design error diagnosis and correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testability analysis and behavioral testing of the Hopfield neural paradigm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implicit permutation enumeration networks and binary decision diagrams reordering
Proceedings of the 48th Design Automation Conference
Reverse engineering architectural feature models
ECSA'11 Proceedings of the 5th European conference on Software architecture
Decomposition-based logic synthesis for PAL-based CPLDs
International Journal of Applied Mathematics and Computer Science
Resolution tunnels for improved SAT solver performance
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
A simple implementation of determinant decision diagram
Proceedings of the International Conference on Computer-Aided Design
Verification of BDD normalization
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Emulation of biological networks in reconfigurable hardware
Proceedings of the 2nd ACM Conference on Bioinformatics, Computational Biology and Biomedicine
Separation of concerns in feature modeling: support and applications
Proceedings of the 11th annual international conference on Aspect-oriented Software Development
GreatSPN enhanced with decision diagram data structures
PETRI NETS'10 Proceedings of the 31st international conference on Applications and Theory of Petri Nets
A scalable threshold logic synthesis method using ZBDDs
Proceedings of the great lakes symposium on VLSI
Computing a hierarchical static order for decision diagram-based representation from p/t nets
Transactions on Petri Nets and Other Models of Concurrency V
An efficient heuristic to identify threshold logic functions
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Deadlock-freedom in component systems with architectural constraints
Formal Methods in System Design
Relation algebras, matrices, and multi-valued decision diagrams
RAMiCS'12 Proceedings of the 13th international conference on Relational and Algebraic Methods in Computer Science
A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits
Analog Integrated Circuits and Signal Processing
BDD-Based Synthesis of Reversible Logic
International Journal of Applied Metaheuristic Computing
Optimizing BDDs for time-series dataset manipulation
Proceedings of the Conference on Design, Automation and Test in Europe
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition
Proceedings of the 50th Annual Design Automation Conference
Boolean equation solving as graph traversal
CATS '06 Proceedings of the Twelfth Computing: The Australasian Theory Symposium - Volume 51
CacBDD: a BDD package with dynamic cache management
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Multi-Core BDD Operations for Symbolic Reachability
Electronic Notes in Theoretical Computer Science (ENTCS)
A simpler counterexample to a long-standing conjecture on the complexity of Bryant's apply algorithm
Information Processing Letters
Journal of Network and Computer Applications
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Efficient manipulation of Boolean functions is an important component of many computer-aided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementation of the if-then-else (ITE) operator. A hash table is used to maintain a strong canonical form in the ROBDD, and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure. A memory function for the recursive ITE algorithm is implemented using a hash-based cache to decrease memory use. Memory function efficiency is improved by using rules that detect when equivalent functions are computed. The usefulness of the package is enhanced by an automatic and low-cost scheme for recycling memory. Experimental results are given to demonstrate why various implementation trade-offs were made. These results indicate that the package described here is significantly faster and more memory-efficient than other ROBDD implementations described in the literature.