A fast mutual exclusion algorithm
ACM Transactions on Computer Systems (TOCS)
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Theoretical Computer Science
BDD variable ordering for interacting finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
A Performance Study of BDD-Based Model Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
ICALP '92 Proceedings of the 19th International Colloquium on Automata, Languages and Programming
On Discretization of Delays in Timed Automata and Digital Circuits
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
Kronos: A Model-Checking Tool for Real-Time Systems
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Some Progress in the Symbolic Verification of Timed Automata
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Probabilistic Model Checking of the IEEE 802.11 Wireless Local Area Network Protocol
PAPM-PROBMIV '02 Proceedings of the Second Joint International Workshop on Process Algebra and Probabilistic Methods, Performance Modeling and Verification
Improvements for the Symbolic Verification of Timed Automata
FORTE '07 Proceedings of the 27th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Making the right cut in model checking data-intensive timed systems
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
SAT-Based Reachability Checking for Timed Automata with Discrete Data
Fundamenta Informaticae - Special Issue on Concurrency Specification and Programming (CS&P)
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
Reachability Analysis for Timed Automata Using Partitioning Algorithms
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2002), Part 2
Model checking for probabilistic timed automata
Formal Methods in System Design
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To develop efficient algorithms for the reachability analysis of timed automata, a promising approach is to use binary decision diagrams (BDDs) as data structure for the representation of the explored state space. The size of a BDD is very sensitive to the ordering of the variables. We use the communication structure to deduce an estimation for the BDD size. In our experiments, this guides the choice of good variable orderings, which leads to an efficient reachability analysis. We develop a discrete semantics for closed timed automata to get a finite state space required by the BDD-based representation and we prove the equivalence to the continuous semantics regarding the set of reachable locations. An upper bound for the size of the BDD representing the transition relation and an estimation for the set of reachable configurations based on the communication structure is given. We implemented these concepts in the verification tool Rabbit [BR00]. Different case studies justify our conjecture: Polynomial reachability analysis seems to be possible for some classes of real-time models, which have a good-natured communication structure.