Theoretical Computer Science
An efficient state space generation for analysis of real-time systems
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Formal Methods in System Design
Bounded Model Checking for Timed Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
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FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Model Checking of Real-Time Reachability Properties Using Abstractions
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Timed Diagnostics for Reachability Properties
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Symbolic Reachability Analysis Based on SAT-Solvers
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Bounded Reachability Checking with Process Semantics
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Verification of Timed Automata via Satisfiability Checking
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Towards Bounded Model Checking for the Universal Fragment of TCTL
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Improvements in BDD-Based Reachability Analysis of Timed Automata
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Lectures on Embedded Systems, European Educational Forum, School on Embedded Systems
A SAT Based Approach for Solving Formulas over Boolean and Linear Mathematical Propositions
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
Lazy Theorem Proving for Bounded Model Checking over Infinite Domains
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
Automated Verification of Infinite State Concurrent Systems
PPAM '01 Proceedings of the th International Conference on Parallel Processing and Applied Mathematics-Revised Papers
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Efficient verification of real-time systems: compact data structure and state-space reduction
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
√erics: a tool for verifying timed automata and estelle specifications
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Checking Reachability Properties for Timed Automata via SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2002), Part 2
Bounded Model Checking for the Universal Fragment of CTL
Fundamenta Informaticae - Concurrency Specification and Programming Workshop (CS&P'2001)
Bounded model checking for knowledge and real time
Proceedings of the fourth international joint conference on Autonomous agents and multiagent systems
Improving the Translation from ECTL to SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
VerICS 2007 - a Model Checker for Knowledge and Real-Time
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Bounded Model Checking for the Existential Fragment of TCTL$_{-G}$ and Diagonal Timed Automata
Fundamenta Informaticae
SAT-Based Reachability Checking for Timed Automata with Discrete Data
Fundamenta Informaticae - Special Issue on Concurrency Specification and Programming (CS&P)
SAT-based Reachability Checking for Timed Automata with Diagonal Constraints
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2004)
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The paper deals with the problem of checking reachability for timed automata. In order to check reachability of a~state satisfying some property, first the transition relation of a timed automaton is unfolded iteratively to some depth and encoded as a propositional formula. Next, the property is translated to a propositional formula and satisfiability of the conjunction of the two defined above formulas is checked. The unfolding of the transition relation can be terminated when either a state satisfying the property has been found or all the states of the timed automaton have been searched. In this paper we propose some improvements of the encoding of the transition relation for timed automata. The improvements are partially based on a new discretization scheme. The efficiency of the improved encoding is strongly supported by the experimental results. We also introduce a method for checking unreachability.