Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Formal Methods in System Design - Special issue on symmetry in automatic verification
Partial order reduction: linear and branching temporal logics and process algebras
POMIV '96 Proceedings of the DIMACS workshop on Partial order methods in verification
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Cliques, Coloring, and Satisfiability: Second DIMACS Implementation Challenge, Workshop, October 11-13, 1993
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Bounded LTL Model Checking with Stable Models
LPNMR '01 Proceedings of the 6th International Conference on Logic Programming and Nonmonotonic Reasoning
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Bounded Reachability Checking with Process Semantics
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Model Checking and Modular Verification
CONCUR '91 Proceedings of the 2nd International Conference on Concurrency Theory
Partial-Order Methods for Temporal Verification
CONCUR '93 Proceedings of the 4th International Conference on Concurrency Theory
Stubborn sets for reduced state space generation
Proceedings of the 10th International Conference on Applications and Theory of Petri Nets: Advances in Petri Nets 1990
Improving Partial Order Reductions for Universal Branching Time Properties
Fundamenta Informaticae
Reducing Model Checking from Multi-valued {\rm CTL}^{\ast} to {\rm CTL}^{\ast}
CONCUR '02 Proceedings of the 13th International Conference on Concurrency Theory
LDYIS: a Framework for Model Checking Security Protocols
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Improving the Translation from ECTL to SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Towards Verification of Java Programs in perICS
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Bounded Model Checking for the Existential Fragment of TCTL$_{-G}$ and Diagonal Timed Automata
Fundamenta Informaticae
Comparing BDD and SAT Based Techniques for Model Checking Chaum's Dining Cryptographers Protocol
Fundamenta Informaticae - SPECIAL ISSUE ON CONCURRENCY SPECIFICATION AND PROGRAMMING (CS&P 2005) Ruciane-Nide, Poland, 28-30 September 2005
On Designated Values in Multi-valued CTL^* Model Checking
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
From Bounded to Unbounded Model Checking for Temporal Epistemic Logic
Fundamenta Informaticae - Multiagent Systems (FAMAS'03)
Verifying Epistemic Properties of Multi-agent Systems via Bounded Model Checking
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2002), Part 2
Checking Reachability Properties for Timed Automata via SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2002), Part 2
ACTLS properties and Bounded Model Checking
Fundamenta Informaticae
A New Translation from ECTL* to SAT
Fundamenta Informaticae - Concurrency Specification and Programming CS&P
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Bounded Model Checking (BMC) has been recently introduced as an efficient verification method for reactive systems. BMC based on SAT methods consists in searching for a counterexample of a particular length and generating a propositional formula that is satisfiable iff such a counterexample exists. This new technique has been introduced by E. Clarke et al. for model checking of linear time temporal logic (LTL). Our paper shows how the concept of bounded model checking can be extended to ACTL (the universal fragment of CTL). The implementation of the algorithm for Elementary Net Systems is described together with the experimental results.