Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Handbook of theoretical computer science (vol. B)
Model-checking in dense real-time
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
Theoretical Computer Science
The benefits of relaxing punctuality
Journal of the ACM (JACM)
Formal Methods in System Design - Special issue on symmetry in automatic verification
Partial order reduction: linear and branching temporal logics and process algebras
POMIV '96 Proceedings of the DIMACS workshop on Partial order methods in verification
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Analysis of Timed Systems Using Time-Abstracting Bisimulations
Formal Methods in System Design
Symbolic Model Checking
Model Checking of Real-Time Reachability Properties Using Abstractions
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Timed Automata with Asynchronous Processes: Schedulability and Decidability
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Partial-Order Methods for Temporal Verification
CONCUR '93 Proceedings of the 4th International Conference on Concurrency Theory
A Space-Efficient On-the-fly Algorithm for Real-Time Model Checking
CONCUR '96 Proceedings of the 7th International Conference on Concurrency Theory
Partial Orders and Verification of Real-Time systems
FTRTFT '96 Proceedings of the 4th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Towards Bounded Model Checking for the Universal Fragment of TCTL
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Logics and Models of Real Time: A Survey
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Lazy Theorem Proving for Bounded Model Checking over Infinite Domains
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
Automated Verification of Infinite State Concurrent Systems
PPAM '01 Proceedings of the th International Conference on Parallel Processing and Applied Mathematics-Revised Papers
On-the-fly symbolic model checking for real-time systems
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Bounded model checking for knowledge and real time
Proceedings of the fourth international joint conference on Autonomous agents and multiagent systems
SAT-based Reachability Checking for Timed Automata with Diagonal Constraints
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2004)
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
Checking Reachability Properties for Timed Automata via SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2002), Part 2
Bounded Model Checking for the Universal Fragment of CTL
Fundamenta Informaticae - Concurrency Specification and Programming Workshop (CS&P'2001)
Improving the Translation from ECTL to SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
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Bounded Model Checking (BMC) is one of the well known SAT based symbolic model checking techniques. It consists in searching for a counterexample of a particular length, and generating a propositional formula that is satisfiable iff such a counterexample exists. The BMC method is feasible for the various classes of temporal logic; in particular it is feasible for TECTL (the existential fragment of Time Computation Tree Logic) and Diagonal-free Timed Automata. The main contribution of the paper is to show that the concept of Bounded Model Checking can be extended to deal with TECTL$_{-G}$ properties of Diagonal Timed Automata. We have implemented our new BMC algorithm, and we present preliminary experimental results, which demonstrate the efficiency of the method.