Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A Structure-preserving Clause Form Translation
Journal of Symbolic Computation
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Symbolic Model Checking
Using induction and BDDs to model check invariants
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
The Industrial Success of Verification Tools Based on Stålmarck's Method
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
A Conjunctively Decomposed Boolean Representation for Symbolic Model Checking
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Detecting false timing paths: experiments on PowerPC microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
Streaming BDD manipulation for large-scale combinatorial problems
Proceedings of the conference on Design, automation and test in Europe
Multi-clock path analysis using propositional satisfiability
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
A hybrid verification approach: getting deep into the design
Proceedings of the 39th annual Design Automation Conference
Satometer:: how much have we searched?
Proceedings of the 39th annual Design Automation Conference
Effective safety property checking using simulation-based sequential ATPG
Proceedings of the 39th annual Design Automation Conference
Model Checking of Safety Properties
Formal Methods in System Design
IEEE Transactions on Computers
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Non-linear quantification scheduling in image computation
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Faster SAT and smaller BDDs via common function structure
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Bounded model checking for the universal fragment of CTL
Fundamenta Informaticae
LPAR '01 Proceedings of the Artificial Intelligence on Logic for Programming
Symbolic Simulation with Approximate Values
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Reachability Analysis Based on SAT-Solvers
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Satisfiability Checking Using Boolean Expression Diagrams
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Model Checking: A Tutorial Overview
MOVEP '00 Proceedings of the 4th Summer School on Modeling and Verification of Parallel Processes
Branching vs. Linear Time: Final Showdown
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Verification of Embedded Software: Problems and Perspectives
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Integrating BDD-Based and SAT-Based Symbolic Model Checking
FroCoS '02 Proceedings of the 4th International Workshop on Frontiers of Combining Systems
Towards Bounded Model Checking for the Universal Fragment of TCTL
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Random 3-SAT: The Plot Thickens
CP '02 Proceedings of the 6th International Conference on Principles and Practice of Constraint Programming
Random 3-SAT and BDDs: The Plot Thickens Further
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking
CL '00 Proceedings of the First International Conference on Computational Logic
CL '00 Proceedings of the First International Conference on Computational Logic
BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Model Checking with Formula-Dependent Abstract Models
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
On Abstraction in Software Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Mixing Forward and Backward Traversals in Guided-Prioritized BDD-Based Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Model checking: a tutorial overview
Modeling and verification of parallel processes
Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
Enhancing Davis Putnam with extended binary clause reasoning
Eighteenth national conference on Artificial intelligence
Handbook of automated reasoning
Improved SAT-based Bounded Reachability Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Random 3-SAT: The Plot Thickens
Constraints
A tutorial introduction to symbolic model checking
Logic for concurrency and synchronisation
Persistent and Quasi-Persistent Lemmas in Propositional Model Elimination
Annals of Mathematics and Artificial Intelligence
Arithmetic Reasoning in DPLL-Based SAT Solving
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A SAT-based algorithm for reparameterization in symbolic simulation
Proceedings of the 41st annual Design Automation Conference
Quantum logic synthesis by symbolic reachability analysis
Proceedings of the 41st annual Design Automation Conference
Using Word-Level Information in Formal Hardware Verification
Automation and Remote Control
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Local Search for Boolean Relations on the Basis of Unit Propagation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
PFGASAT" A Genetic SAT Solver Combining Partitioning and Fuzzy Strategies
COMPSAC '04 Proceedings of the 28th Annual International Computer Software and Applications Conference - Volume 01
Annals of Mathematics and Artificial Intelligence
Success-Driven Learning in ATPG for Preimage Computation
IEEE Design & Test
Proof-guided underapproximation-widening for multi-process systems
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
A Faster Counterexample Minimization Algorithm Based on Refutation Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Efficient Sequential SAT Solver With Improved Search Strategies
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Normalization at the arithmetic bit level
Proceedings of the 42nd annual Design Automation Conference
Efficient SAT solving: beyond supercubes
Proceedings of the 42nd annual Design Automation Conference
Bounded model checking for knowledge and real time
Proceedings of the fourth international joint conference on Autonomous agents and multiagent systems
Model Checking C Programs Using F-SOFT
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
State Set Management for SAT-based Unbounded Model Checking
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Checking consistency of C and Verilog using predicate abstraction and induction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
ATPG-based preimage computation: efficient search space pruning with ZBDD
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
A comparison of BDDs, BMC, and sequential SAT for model checking
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Word level functional coverage computation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Discovering the input assumptions in specification refinement coverage
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
SAT-based sequential depth computation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Hardware verification using ANSI-C programs as a reference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Integration of supercubing and learning in a SAT solver
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A fast counterexample minimization approach with refutation analysis and incremental SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient LTL compilation for SAT-based model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient Symmetry Breaking for Boolean Satisfiability
IEEE Transactions on Computers
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
Mining global constraints for improving bounded sequential equivalence checking
Proceedings of the 43rd annual Design Automation Conference
GASAT: a genetic local search algorithm for the satisfiability problem
Evolutionary Computation
Symbolic Techniques in Satisfiability Solving
Journal of Automated Reasoning
B-Cubing: New Possibilities for Efficient SAT-Solving
IEEE Transactions on Computers
IEEE Transactions on Computers
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging
IEEE Transactions on Computers
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
ACTLS properties and Bounded Model Checking
Fundamenta Informaticae
Reducing verification overhead with RTL slicing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Verification of SpecC using predicate abstraction
Formal Methods in System Design
Bounded model checking of infinite state systems
Formal Methods in System Design
Accelerating high-level bounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Accurate timing analysis using SAT and pattern-dependent delay models
Proceedings of the conference on Design, automation and test in Europe
BerkMin: A fast and robust Sat-solver
Discrete Applied Mathematics
Using SAT-based techniques in power estimation
Microelectronics Journal
Boosting interpolation with dynamic localized abstraction and redundancy removal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bounded model checking for knowledge and real time
Artificial Intelligence
Computation of minimal counterexamples by using black box techniques and symbolic methods
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Formal verification at higher levels of abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Bounded Model Checking for the Existential Fragment of TCTL_{-G} and Diagonal Timed Automata
Fundamenta Informaticae
Efficient SAT-based bounded model checking for software verification
Theoretical Computer Science
Model Checking: Back and Forth between Hardware and Software
Verified Software: Theories, Tools, Experiments
A Symbolic Model Checking Framework for Safety Analysis, Diagnosis, and Synthesis
Model Checking and Artificial Intelligence
Verification Technology Transfer
25 Years of Model Checking
A Direct Algorithm for Multi-valued Bounded Model Checking
ATVA '08 Proceedings of the 6th International Symposium on Automated Technology for Verification and Analysis
Automated abstraction by incremental refinement in interpolant-based model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Improving the Translation from ECTL to SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Trading-off SAT search and variable quantifications for effective unbounded model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Enhancing SAT-based sequential depth computation by pruning search space
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Partitioned PLTL model-checking for refined transition systems
Information and Computation
Direct model checking matrix algorithm
Journal of Computer Science and Technology
A new Approach for Solving Satisfiability Problems with Qualitative Preferences
Proceedings of the 2008 conference on ECAI 2008: 18th European Conference on Artificial Intelligence
Hybrid BDD and All-SAT Method for Model Checking
Languages: From Formal to Natural
Boundary Points and Resolution
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
New Encodings of Pseudo-Boolean Constraints into CNF
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
Automated deduction for verification
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
Improved bounded model checking for the universal fragment of CTL
Journal of Computer Science and Technology
SymChaff: a structure-aware satisfiability solver
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 1
Propositional independence: formula-variable independence and forgetting
Journal of Artificial Intelligence Research
Towards understanding and harnessing the potential of clause learning
Journal of Artificial Intelligence Research
SATzilla: portfolio-based algorithm selection for SAT
Journal of Artificial Intelligence Research
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
Efficient symmetry breaking for boolean satisfiability
IJCAI'03 Proceedings of the 18th international joint conference on Artificial intelligence
Understanding the power of clause learning
IJCAI'03 Proceedings of the 18th international joint conference on Artificial intelligence
Automated verification: graphs, logic, and automata
IJCAI'03 Proceedings of the 18th international joint conference on Artificial intelligence
Hybrid testing and verification techniques for a cognitive radio system
SEA '07 Proceedings of the 11th IASTED International Conference on Software Engineering and Applications
PN code acquisition using Boolean satisfiability techniques
WCNC'09 Proceedings of the 2009 IEEE conference on Wireless Communications & Networking Conference
LTL Model Checking for Recursive Programs
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT-based Induction for Temporal Safety Properties
Electronic Notes in Theoretical Computer Science (ENTCS)
Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Proving unreachability using bounded model checking
Proceedings of the 3rd India software engineering conference
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CSCWD'06 Proceedings of the 10th international conference on Computer supported cooperative work in design III
Bounded model checking for past LTL
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Hybrid systems: from verification to falsification
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Limitations of restricted branching in clause learning
CP'07 Proceedings of the 13th international conference on Principles and practice of constraint programming
Complete SAT-based model checking for context-free processes
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
3-valued circuit SAT for STE with automatic refinement
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Computation of satisfiability degree based on CNF
FSKD'09 Proceedings of the 6th international conference on Fuzzy systems and knowledge discovery - Volume 6
Partitioning interpolant-based verification for effective unbounded model checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesizing complementary circuits automatically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability
Proceedings of the Conference on Design, Automation and Test in Europe
Increasing the accuracy of SAT-based debugging
Proceedings of the Conference on Design, Automation and Test in Europe
Bounded Parametric Verification for Distributed Time Petri Nets with Discrete-Time Semantics
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
A novel SAT-based approach to the task graph cost-optimal scheduling problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Graph transformation units guided by a sat solver
ICGT'10 Proceedings of the 5th international conference on Graph transformations
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bounded parametric model checking for elementary net systems
Transactions on Petri nets and other models of concurrency IV
SAT-based (parametric) reachability for a class of distributed time Petri nets
Transactions on Petri nets and other models of concurrency IV
Cause clue clauses: error localization using maximum satisfiability
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems
Journal of Electronic Testing: Theory and Applications
SAT-based semiformal verification of hardware
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Formal hardware/software co-verification by interval property checking with abstraction
Proceedings of the 48th Design Automation Conference
Bug-Assist: assisting fault localization in ANSI-C programs
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
The BMC method for the existential part of RTCTLK and interleaved interpreted systems
EPIA'11 Proceedings of the 15th Portugese conference on Progress in artificial intelligence
Incremental preprocessing methods for use in BMC
Formal Methods in System Design
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
Abstraction and refinement in model checking
FMCO'05 Proceedings of the 4th international conference on Formal Methods for Components and Objects
Poster: towards formal verification of DIFC policies
Proceedings of the 18th ACM conference on Computer and communications security
Bounded model checking for GSMP models of stochastic real-time systems
HSCC'06 Proceedings of the 9th international conference on Hybrid Systems: computation and control
Verifying very large industrial circuits using 100 processes and beyond
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Treewidth in verification: local vs. global
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Search vs. symbolic techniques in satisfiability solving
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Fifty-five solvers in vancouver: the SAT 2004 competition
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Managing SAT inconsistencies with HUMUS
Proceedings of the Sixth International Workshop on Variability Modeling of Software-Intensive Systems
Optimizations for compiling declarative models into boolean formulas
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Minimizing counterexample with unit core extraction and incremental SAT
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Verification of an error correcting code by abstract interpretation
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Minimizing generalized büchi automata
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
DiVer: SAT-based model checking platform for verifying large scale systems
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Solving CSP including a universal quantification
MOZ'04 Proceedings of the Second international conference on Multiparadigm Programming in Mozart/Oz
Symmetry reduction in SAT-based model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Repairing structurally complex data
SPIN'05 Proceedings of the 12th international conference on Model Checking Software
Proving ∀µ-calculus properties with SAT-based model checking
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
The big deal: applying constraint satisfaction technologies where it makes the difference
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
Sanity checks in formal verification
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
On the satisfiability of modular arithmetic formulae
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
The sweep-line state space exploration method
Theoretical Computer Science
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
SBMC: symmetric bounded model checking
VECoS'10 Proceedings of the Fourth international conference on Verification and Evaluation of Computer and Communication Systems
Towards efficient MUS extraction
AI Communications - 18th RCRA International Workshop on “Experimental evaluation of algorithms for solving problems with combinatorial explosion”
Evaluating component solver contributions to portfolio-based algorithm selectors
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Efficient SAT solving under assumptions
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
A comparison of strategies for tolerating inconsistencies during decision-making
Proceedings of the 16th International Software Product Line Conference - Volume 1
Improving the Translation from ECTL to SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Bounded Model Checking for the Existential Fragment of TCTL$_{-G}$ and Diagonal Timed Automata
Fundamenta Informaticae
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
ACTLS properties and Bounded Model Checking
Fundamenta Informaticae
Bounded Model Checking for the Universal Fragment of CTL
Fundamenta Informaticae - Concurrency Specification and Programming Workshop (CS&P'2001)
From graph transformation units via minisat to GrGen.NET
AGTIVE'11 Proceedings of the 4th international conference on Applications of Graph Transformations with Industrial Relevance
Complete SAT solver based on set theory
ICICA'12 Proceedings of the Third international conference on Information Computing and Applications
A compact encoding of pseudo-boolean constraints into SAT
KI'12 Proceedings of the 35th Annual German conference on Advances in Artificial Intelligence
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Optimization techniques for craig interpolant compaction in unbounded model checking
Proceedings of the Conference on Design, Automation and Test in Europe
Thread-based multi-engine model checking for multicore platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verifying refutations with extended resolution
CADE'13 Proceedings of the 24th international conference on Automated Deduction
Soundness of inprocessing in clause sharing SAT solvers
SAT'13 Proceedings of the 16th international conference on Theory and Applications of Satisfiability Testing
Improving glucose for incremental SAT solving with assumptions: application to MUS extraction
SAT'13 Proceedings of the 16th international conference on Theory and Applications of Satisfiability Testing
Automated reencoding of boolean formulas
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Autonomous Agents and Multi-Agent Systems
Towards Automatic Composition of Web Services: SAT-Based Concretisation of Abstract Scenarios
Fundamenta Informaticae
A New Translation from ECTL* to SAT
Fundamenta Informaticae - Concurrency Specification and Programming CS&P
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