Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Improved SAT-based Bounded Reachability Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Iterative Abstraction using SAT-based BMC with Proof Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Lazy Constraints and SAT Heuristics for Proof-Based Abstraction
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Verification of Embedded Memory Systems using Efficient Memory Modeling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Beyond safety: customized SAT-based model checking
Proceedings of the 42nd annual Design Automation Conference
Model Checking C Programs Using F-SOFT
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Accelerating high-level bounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Exploring different constraint-based modelings for program verification
CP'07 Proceedings of the 13th international conference on Principles and practice of constraint programming
From hardware verification to software verification: re-use and re-learn
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
F-SOFT: software verification platform
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Exploration of the capabilities of constraint programming for software verification
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Secure two-party computations in ANSI C
Proceedings of the 2012 ACM conference on Computer and communications security
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We present a SAT-based model checking platform (DiVer) based on robust and scalable algorithms that are tightly integrated for verifying large scale industry designs. DiVer houses various SAT-based engines each targeting capacity and performance issues inherent in verifying large designs. The engines with their respective roles are as follows: Bounded Model Checking (BMC) and Distributed BMC over a network of workstations for falsification, Proof-based Iterative Abstraction (PBIA) for model reduction, SAT-based Unbounded Model Checking and Induction for proofs, Efficient Memory Modeling (EMM) and its combination with PBIA in BMC for verifying embedded memory systems with multiple memories (with multiple ports and arbitrary initial state). Using several industrial case studies, we describe the interplay of these engines highlighting their contribution at each step of verification. DiVer has matured over 3 years and is being used extensively in several industry settings. Due to an efficient and flexible infrastructure, it provides a very productive verification environment for research and development.