Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
The Quest for Efficient Boolean Satisfiability Solvers
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Lazy Theorem Proving for Bounded Model Checking over Infinite Domains
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
LICS '97 Proceedings of the 12th Annual IEEE Symposium on Logic in Computer Science
Improved SAT-based Bounded Reachability Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ICSM '03 Proceedings of the International Conference on Software Maintenance
Beyond safety: customized SAT-based model checking
Proceedings of the 42nd annual Design Automation Conference
Compilers: Principles, Techniques, and Tools (2nd Edition)
Compilers: Principles, Techniques, and Tools (2nd Edition)
Deciding separation logic formulae by SAT and incremental negative cycle elimination
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Using statically computed invariants inside the predicate abstraction and refinement loop
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
DiVer: SAT-based model checking platform for verifying large scale systems
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
DPLL(T) with exhaustive theory propagation and its application to difference logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
Tunneling and slicing: towards scalable BMC
Proceedings of the 45th annual Design Automation Conference
Simulation-directed invariant mining for software verification
Proceedings of the conference on Design, automation and test in Europe
Completeness in SMT-based BMC for software programs
Proceedings of the conference on Design, automation and test in Europe
Efficient Modeling of Concurrent Systems in BMC
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
Scaling up the formal verification of Lustre programs with SMT-based techniques
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT($\mathcal{LIA}$)
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
d-TSR: Parallelizing SMT-Based BMC Using Tunnels over a Distributed Framework
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
ACM Computing Surveys (CSUR)
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
From hardware verification to software verification: re-use and re-learn
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
SMT-based bounded model checking for multi-threaded software in embedded systems
Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering - Volume 2
A precise memory model for low-level bounded model checking
SSV'10 Proceedings of the 5th international conference on Systems software verification
A dynamic constraint-based BMC strategy for generating counterexamples
Proceedings of the 2011 ACM Symposium on Applied Computing
Verifying multi-threaded software using smt-based context-bounded model checking
Proceedings of the 33rd International Conference on Software Engineering
Propelling SAT and SAT-based BMC using careset
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Efficient state space exploration: interleaving stateless and state-based model checking
Proceedings of the International Conference on Computer-Aided Design
Boosting local consistency algorithms over floating-point numbers
CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming
Predicting serializability violations: SMT-Based search vs. DPOR-Based search
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Scaling RTL property checking using feasible path analysisand decomposition
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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SAT-based Bounded Model Checking (BMC) has been found promising in finding deep bugs in industry designs and scaling well with design sizes. However, it has limitations due to requirement of finite data paths, inefficient translations and loss of high-level design information during the BMC problem formulation. These shortcomings inherent in Boolean-level BMC can be avoided by using high-level BMC. We propose a novel framework for high-level BMC, which includes several techniques that extract high-level design information from EFSM models to make the verification model "BMC friendly", and use it on-the-fly to simplify the BMC problem instances. Such techniques overcome the inherent limitations of Boolean-level BMC, while allowing integration of state-of-the-art techniques for BMC. In our controlled experiments we found signficant performance improvements achievable by the proposed techniques.