Introduction to algorithms
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
The Cassowary linear arithmetic constraint solving algorithm
ACM Transactions on Computer-Human Interaction (TOCHI)
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
Proceedings of the 39th annual Design Automation Conference
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
Proceedings of the 40th annual Design Automation Conference
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Accelerating high-level bounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
SAT-Based Scalable Formal Verification Solutions (Series on Integrated Circuits and Systems)
SAT-Based Scalable Formal Verification Solutions (Series on Integrated Circuits and Systems)
Deciding bit-vector arithmetic with abstraction
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
BAT: the bit-level analysis tool
CAV'07 Proceedings of the 19th international conference on Computer aided verification
A decision procedure for bit-vectors and arrays
CAV'07 Proceedings of the 19th international conference on Computer aided verification
A lazy and layered SMT(BV) solver for hard industrial verification problems
CAV'07 Proceedings of the 19th international conference on Computer aided verification
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
F-SOFT: software verification platform
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
DPLL(T) with exhaustive theory propagation and its application to difference logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
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For the verification of complex designs, one often needs to solve decision problems containing integer non-linear constraints. Due to the undecidability of the problem, one usually considers bounded integers and then either linearizes the problem into a SMT($\mathcal{LIA}$) problem (i.e., the theory of linear integer arithmetic with Boolean constraints) or bit-blasts into a SAT problem. We present a novel way of linearizing those constraints, and then show how the proposed encoding to a SMT($\mathcal{LIA}$) problem can be integrated into an incremental lazy bounding and refinement procedure (LBR ) that leverages on the success of the state-of-the-art SMT($\mathcal{LIA}$) solvers. The most important feature of our LBR procedure is that the formula need not be re-encoded at every step of the procedure but rather, only bounds on variables need to be asserted/retracted, which are very efficiently supported by the recent SMT($\mathcal{LIA}$) solvers. In a series of controlled experiments, we show the effectiveness of our linearization encoding and LBR procedure in reducing the SMT solve time. We observe similar effectiveness of LBR procedure when used in a software verification framework applied on industry benchmarks.