Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Some results and experiments in programming techniques for propositional logic
Computers and Operations Research - Special issue: Applications of integer programming
Efficient generation of test patterns using Boolean satisfiability
Efficient generation of test patterns using Boolean satisfiability
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improvements to propositional satisfiability search algorithms
Improvements to propositional satisfiability search algorithms
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Algorithms for solving Boolean satisfiability in combinational circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
A BDD-based satisfiability infrastructure using the unate recursive paradigm
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Constraint Slving for Test Case Generation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Coverage-directed validation of hardware models
Coverage-directed validation of hardware models
Explicit and implicit algorithms for binate covering problems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
Arithmetic Reasoning in DPLL-Based SAT Solving
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Using Word-Level Information in Formal Hardware Verification
Automation and Remote Control
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Normalization at the arithmetic bit level
Proceedings of the 42nd annual Design Automation Conference
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Verification of embedded systems based on interval analysis
International Journal of Parallel Programming
EHSAT: an efficient RTL satisfiability solver using an extended DPLL procedure
Proceedings of the 44th annual Design Automation Conference
Verification of arithmetic datapaths using polynomial function models and congruence solving
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT($\mathcal{LIA}$)
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integration, the VLSI Journal
Encoding RTL Constructs for MathSAT: a Preliminary Report
Electronic Notes in Theoretical Computer Science (ENTCS)
A lazy and layered SMT(BV) solver for hard industrial verification problems
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Building efficient decision procedures on top of SAT solvers
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Constraint satisfaction over bit-vectors
CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming
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