IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Functional Test Generation using Constraint Logic Programming
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Structural Testing of Executables
ICST '08 Proceedings of the 2008 International Conference on Software Testing, Verification, and Validation
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
BTOR: bit-precise modelling of word-level problems for model checking
SMT '08/BPR '08 Proceedings of the Joint Workshops of the 6th International Workshop on Satisfiability Modulo Theories and 1st International Workshop on Bit-Precise Reasoning
Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Deciding bit-vector arithmetic with abstraction
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Code-based test generation for validation of functional processor descriptions
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
A decision procedure for bit-vectors and arrays
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Constraint integer programming: a new approach to integrate CP and MIP
CPAIOR'08 Proceedings of the 5th international conference on Integration of AI and OR techniques in constraint programming for combinatorial optimization problems
Bit-vector algorithms for binary constraint satisfaction and subgraph isomorphism
Journal of Experimental Algorithmics (JEA)
An alternative to SAT-Based approaches for bit-vectors
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
| Hi-index | 0.00 |
Reasoning over bit-vectors arises in a variety of applications in verification and cryptography. This paper presents a bit-vector domain for constraint programming and its associated filtering algorithms. The domain supports all the traditional bit operations and correctly models modulo-arithmetic and overflows. The domain implementation uses bit operations of the underlying architecture, avoiding the drawback of a bit-blasting approach that associates a variable with each bit. The filtering algorithms implement either domain consistency on the bit-vector domain or bit consistency, a new consistency notion introduced in this paper. Filtering algorithms for logical and structural constraints typically run in constant time, while arithmetic constraints such as addition run in time linear in the size of the bit-vectors. The paper also discusses how to channel bit-vector variables with an integer variable.