Hacker's Delight
Boosting Verification by Automatic Tuning of Decision Procedures
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Proceedings of the 46th Annual Design Automation Conference
Deciding bit-vector arithmetic with abstraction
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Applying logic synthesis for speeding up SAT
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
BAT: the bit-level analysis tool
CAV'07 Proceedings of the 19th international conference on Computer aided verification
A decision procedure for bit-vectors and arrays
CAV'07 Proceedings of the 19th international conference on Computer aided verification
A lazy and layered SMT(BV) solver for hard industrial verification problems
CAV'07 Proceedings of the 19th international conference on Computer aided verification
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Small formulas for large programs: on-line constraint simplification in scalable static analysis
SAS'10 Proceedings of the 17th international conference on Static analysis
A real-world benchmark model for testing concurrent real-time systems in the automotive domain
ICTSS'11 Proceedings of the 23rd IFIP WG 6.1 international conference on Testing software and systems
Effective word-level interpolation for software verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
An SMT-Based discovery algorithm for c-nets
PETRI NETS'12 Proceedings of the 33rd international conference on Application and Theory of Petri Nets
Constraint satisfaction over bit-vectors
CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming
Enhancing symbolic execution with built-in term rewriting and constrained lazy initialization
Proceedings of the 2013 9th Joint Meeting on Foundations of Software Engineering
Automating exercise generation: a step towards meeting the MOOC challenge for embedded systems
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education
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We present the key ideas in the design and implementation of Beaver, an SMT solver for quantifier-free finite-precision bit-vector logic (QF_BV). Beaver uses an eager approach, encoding the original SMT problem into a Boolean satisfiability (SAT) problem using a series of word-level and bit-level transformations. In this paper, we describe the most effective transformations, such as propagating constants and equalities at the word-level, and using and-inverter graph rewriting techniques at the bit-level. We highlight implementation details of these transformations that distinguishes Beaver from other solvers. We present an experimental analysis of the effectiveness of Beaver's techniques on both hardware and software benchmarks with a selection of back-end SAT solvers. Beaver is an open-source tool implemented in Ocaml, usable with any back-end SAT engine, and has a well-documented extensible code base that can be used to experiment with new algorithms and techniques.