Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DAG-aware circuit compression for formal verification
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Clause form conversions for boolean circuits
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Effective preprocessing in SAT through variable and clause elimination
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Benchmarking SAT solvers for bounded model checking
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Improvements to Technology Mapping for LUT-Based FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential mapping with priority cuts
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Recording synthesis history for sequential verification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Proceedings of the 46th Annual Design Automation Conference
SAT-Solving in Practice, with a Tutorial Example from Supervisory Control
Discrete Event Dynamic Systems
Faster SAT solving with better CNF generation
Proceedings of the Conference on Design, Automation and Test in Europe
SAT-based model checking without unrolling
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
A single-instance incremental SAT formulation of proof- and counterexample-based abstraction
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Genetic Programming and Evolvable Machines
A real-world benchmark model for testing concurrent real-time systems in the automotive domain
ICTSS'11 Proceedings of the 23rd IFIP WG 6.1 international conference on Testing software and systems
MDG-SAT: an automated methodology for efficient safety checking
International Journal of Critical Computer-Based Systems
Gateway decompositions for constrained reachability problems
SEA'10 Proceedings of the 9th international conference on Experimental Algorithms
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
ICFEM'12 Proceedings of the 14th international conference on Formal Engineering Methods: formal methods and software engineering
GLA: gate-level abstraction revisited
Proceedings of the Conference on Design, Automation and Test in Europe
Automated reencoding of boolean formulas
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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SAT solvers are often challenged with very hard problems that remain unsolved after hours of CPU time. The research community meets the challenge in two ways: (1) by improving the SAT solver technology, for example, perfecting heuristics for variable ordering, and (2) by inventing new ways of constructing simpler SAT problems, either using domain specific information during the translation from the original problem to CNF, or by applying a more universal CNF simplification procedure after the translation. This paper explores preprocessing of circuit-based SAT problems using recent advances in logic synthesis. Two fast logic synthesis techniques are considered: DAG-aware logic minimization and a novel type of structural technology mapping, which reduces the size of the CNF derived from the circuit. These techniques are experimentally compared to CNF-based preprocessing. The conclusion is that the proposed techniques are complementary to CNF-based preprocessing and speedup SAT solving substantially on industrial examples.