Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Xmap: A technology mapper for table-lookup field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A heuristic method for FPGA technology mapping based on the edge visibility
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous depth and area minimization in LUT-based FPGA mapping
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Optimal clock period FPGA technology mapping for sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
FPGA Technology Mapping for Power Minimization
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Low-power technology mapping for FPGA architectures with dual supply voltages
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient LUT-based FPGA technology mapping for power minimization
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improvements to technology mapping for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Optimal simultaneous mapping and clustering for FPGA delay optimization
Proceedings of the 43rd annual Design Automation Conference
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
New timing and routability driven placement algorithms for FPGA synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
GlitchMap: an FPGA technology mapper for low power considering glitches
Proceedings of the 44th annual Design Automation Conference
DDBDD: delay-driven BDD synthesis for FPGAs
Proceedings of the 44th annual Design Automation Conference
How much can logic perturbation help from netlist to final routing for FPGAs
Proceedings of the 44th annual Design Automation Conference
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Combinational and sequential mapping with priority cuts
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
WireMap: FPGA technology mapping for improved routability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Mapping for better than worst-case delays in LUT-based FPGA designs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Efficient ASIP design for configurable processors with fine-grained resource sharing
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
FPGA area reduction by multi-output function based sequential resynthesis
Proceedings of the 45th annual Design Automation Conference
Rapid design of area-efficient custom instructions for reconfigurable embedded processing
Journal of Systems Architecture: the EUROMICRO Journal
Smart Enumeration: A Systematic Approach to Exhaustive Search
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
FPGA technology mapping with encoded libraries andstaged priority cuts
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Scalable don't-care-based logic optimization and resynthesis
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
FPCNA: a field programmable carbon nanotube array
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Boolean factoring and decomposition of logic networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Physical optimization for FPGAs using post-placement topology rewriting
Proceedings of the 2009 international symposium on Physical design
A routing approach to reduce glitches in low power FPGAs
Proceedings of the 2009 international symposium on Physical design
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
On K-LUT based FPGA optimum delay and optimal area mapping
MACMESE'08 Proceedings of the 10th WSEAS international conference on Mathematical and computational methods in science and engineering
Design and synthesis of programmable logic block with mixed LUT and macrogate
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and evaluation of a carbon nanotube-based programmable architecture
International Journal of Parallel Programming
Global delay optimization using structural choices
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
A routing approach to reduce glitches in low power FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Applying logic synthesis for speeding up SAT
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
Technology mapping and clustering for FPGA architectures with dual supply voltages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Area-efficient FPGA logic elements: architecture and synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
SETmap: a soft error tolerant mapping algorithm for FPGA designs with low power
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Scalable don't-care-based logic optimization and resynthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
FPGA technology mapping with encoded libraries and staged priority cuts
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Architecture and performance evaluation of 3D CMOS-NEM FPGA
Proceedings of the System Level Interconnect Prediction Workshop
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Rapid evaluation of custom instruction selection approaches with FPGA estimation
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.01 |
In This work we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chip performance constraint. This is a well-studied topic and a very difficult task (NP-hard). The contributions of This work are as follows: (i) we consider the potential node duplications during the cut enumeration/generation procedure so the mapping costs encoded in the cuts drive the area-optimization objective more effectively; (ii) after the timing constraint is determined, we will relax the non-critical paths by searching the solution space considering both local and global optimality information to minimize mapping area; (iii) an iterative cut selection procedure is carried out that further explores and perturbs the solution space to improve solution quality. We guarantee optimal mapping depth under the unit delay model. Experimental results show that our mapping algorithm, named DAOmap, produces significant quality and runtime improvements. Compared to the state-of-the-art depth-optimal, area minimization mapping algorithm CutMap (Cong and Hwan, 1995), DAOmap is 16.02% better on area and runs 24.2X faster on average when both algorithms are mapping to FPGAs using LUTs of five inputs. LUTs of other inputs are also used for comparisons.