On area/depth trade-off in LUT-based FPGA technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Simultaneous depth and area minimization in LUT-based FPGA mapping
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Logic decomposition during technology mapping
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A new retiming-based technology mapping algorithm for LUT-based FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A new enhanced constructive decomposition and mapping algorithm
Proceedings of the 40th annual Design Automation Conference
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 2005 international symposium on Physical design
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimality study of logic synthesis for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Improvements to technology mapping for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Efficient SAT-based Boolean matching for FPGA technology mapping
Proceedings of the 43rd annual Design Automation Conference
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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We propose a new resynthesis algorithm for FPGA area reduction. In contrast to existing resynthesis techniques, which consider only single-output Boolean functions and the combinational portion of a circuit, we consider multi-output functions and retiming, and develop effective algorithms that incorporate recent improvements to SAT-based Boolean matching. Our experimental results show that with the optimal logic depth, the resynthesis considering multi-output functions reduces area by up to 0.4% compared to the one considering single-output functions, and the sequential resynthesis reduces area by up to 10% compared to combinational resynthesis when both consider multi-output functions. Furthermore, our proposed resynthesis algorithm reduces area by up to 16% compared to the best existing academic technology mapper, Berkeley ABC.