Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Xmap: A technology mapper for table-lookup field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A heuristic method for FPGA technology mapping based on the edge visibility
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous depth and area minimization in LUT-based FPGA mapping
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
Optimality, scalability and stability study of partitioning and placement algorithms
Proceedings of the 2003 international symposium on Physical design
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
An area-optimality study of floorplanning
Proceedings of the 2004 international symposium on Physical design
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimality and Stability Study of Timing-Driven Placement Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
Evaluation of placer suboptimality via zero-change netlist transformations
Proceedings of the 2005 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
FPGA area reduction by multi-output function based sequential resynthesis
Proceedings of the 45th annual Design Automation Conference
Benchmarking in digital circuit design automation
WSEAS Transactions on Circuits and Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
MO-pack: many-objective clustering for FPGA CAD
Proceedings of the 48th Design Automation Conference
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FPGA logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few years has slowed considerably (with some notable exceptions). It seems natural to then question whether the current logic synthesis and technology mapping algorithms for FPGA designs are producing near-optimal solutions. Although there are many empirical studies that compare different FPGA synthesis/mapping algorithms, little is known about how far these algorithms are from the optimal (recall that both logic optimization and technology mapping problems are NP-hard if we consider area optimization in addition to delay/depth optimization). In this paper we present a novel method for constructing arbitrarily large circuits that have known optimal solutions after technology mapping. Using these circuits and their derivatives (called LEKO and LEKU, respectively), we show that although leading FPGA technology mapping algorithms can produce close to optimal solutions, the results from the entire logic synthesis flow (logic optimization + mapping) are far from optimal. The best industrial and academic FPGA synthesis flows are around 140 times larger in terms of area on average, and in some cases as much as 500 times larger on LEKU examples. These results clearly indicate that there is much room for further research and improvement in FPGA synthesis.