Chortle-crf: Fast technology mapping for lookup table-based FPGAs

TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Area and delay mapping for table-look-up based field programmable gate arrays

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Maximal reduction of lookup-table based FPGAs

EURO-DAC '92 Proceedings of the conference on European design automation

A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping

EURO-DAC '92 Proceedings of the conference on European design automation

On area/depth trade-off in LUT-based FPGA technology mapping

DAC '93 Proceedings of the 30th international Design Automation Conference

Sequential synthesis for table look up programmable gate arrays

DAC '93 Proceedings of the 30th international Design Automation Conference

BDD based decomposition of logic functions with application to FPGA synthesis

DAC '93 Proceedings of the 30th international Design Automation Conference

A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Layout driven logic synthesis for FPGAs

DAC '94 Proceedings of the 31st annual Design Automation Conference

A hardware environment for prototyping and partitioning based on multiple FPGAs

EURO-DAC '94 Proceedings of the conference on European design automation

On nominal delay minimization in LUT-based FPGA technology mapping

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Technology mapping for field-programmable gate arrays using integer programming

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Area-speed tradeoffs for hierarchical field-programmable gate arrays

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

Technology mapping of sequential circuits for LUT-based FPGAs for performance

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Optimal clock period FPGA technology mapping for sequential circuits

DAC '96 Proceedings of the 33rd annual Design Automation Conference

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

A new method to express functional permissibilities for LUT based FPGAs and its applications

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Compilation of optimized OBDD-algorithms

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Cube-packing and two-level minimization

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Combining technology mapping and placement for delay-optimization in FPGA designs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

A new retiming-based technology mapping algorithm for LUT-based FPGAs

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

Technology mapping for FPGAs with embedded memory blocks

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

Technology mapping for large complex PLDs

DAC '98 Proceedings of the 35th annual Design Automation Conference

Exact tree-based FPGA technology mapping for logic blocks with independent LUTs

DAC '98 Proceedings of the 35th annual Design Automation Conference

Optimal clock period FPGA technology mapping for sequential circuits

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Cut ranking and pruning: enabling a general and efficient FPGA mapping solution

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

A tutorial on logic synthesis for lookup-table based FPGAs

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Rectification method for lookup-table type FPGA's

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Technology mapping for k/m-macrocell based FPGAs

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Depth optimal incremental mapping for field programmable gate arrays

Proceedings of the 37th Annual Design Automation Conference

Performance-driven mapping for CPLD architectures

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays

A new techology mapping for CPLD under the time constraint

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Power minization in LUT-based FPGA technology mapping

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

BDD-based logic synthesis for LUT-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization

IEEE Design & Test

Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping

IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing

LUT-based FPGA Technology Mapping using Permissible Functions

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Some Recent Advances in Software and Hardware Logic Simulation

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Power minimization algorithms for LUT-based FPGA technology mapping

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A synthesis oriented omniscient manual editor

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

Incremental physical resynthesis for timing optimization

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Technology mapping and architecture evalution for k/m-macrocell-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

An efficient algorithm for finding the minimal-area FPGA technology mapping

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Floorplan design for multi-million gate FPGAs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Optimality study of logic synthesis for LUT-based FPGAs

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

A technology mapping algorithm for heterogeneous FPGAs

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Efficient LUT-based FPGA technology mapping for power minimization

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Optimal simultaneous mapping and clustering for FPGA delay optimization

Proceedings of the 43rd annual Design Automation Conference

GlitchMap: an FPGA technology mapper for low power considering glitches

Proceedings of the 44th annual Design Automation Conference

FPGA Design Automation: A Survey

Foundations and Trends in Electronic Design Automation

A framework for layout-level logic restructuring

Proceedings of the 2008 international symposium on Physical design

Smart Enumeration: A Systematic Approach to Exhaustive Search

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

On area/depth trade-off in LUT-based FPGA technology mapping

IEEE Transactions on Very Large Scale Integration (VLSI) Systems