Introduction to algorithms
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Technology mapping for k/m-macrocell based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Technology mapping issues for an FPGA with lookup tables and PLA-like blocks
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Performance-driven mapping for CPLD architectures
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A new techology mapping for CPLD under the time constraint
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Macrocell Architectures for Product Term Embedded Memory Arrays
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Logic synthesis for PAL-based CPLD-s based on two-stage decomposition
Journal of Systems and Software
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Logic synthesis based on decomposition for CPLDs
Microprocessors & Microsystems
Decomposition-based logic synthesis for PAL-based CPLDs
International Journal of Applied Mathematics and Computer Science
Area and speed oriented synthesis of FSMs for PAL-based CPLDs
Microprocessors & Microsystems
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In this paper we present a new technology mapping algorithm for use with complex PLDs (CPLDs), which consists of a large number of PLA-style logic blocks. Although the traditional synthesis approach for such devices uses two-level minimization, the complexity of recently-produced CPLDs has resulted in a trend toward multi-level synthesis. We describe an approach that allows existing multi-level synthesis techniques [13] to be adapted to produce circuits that are well-suited for implementation in CPLDs. Our algorithm produces circuits that require up to 90% fewer logic blocks than the circuits produced by a recently-published algorithm.