A new techology mapping for CPLD under the time constraint

Authors:
Jae-Jin Kim;Hi-Seok Kim;Chi-Ho Lin
Affiliations:
Dept. of Electronic Engineering, Chongji University, Naedok-dong, Sangdang-gu Chongju-shi, Korea 360-764;-;Dept. of Computer Science, Semyung University and Dept. of Electronic Engineering, Chongju Unoversity, Naedok-dong, Sangdang-gu Chongju-shi, Korea
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

Citing 2
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Decomposition-based logic synthesis for PAL-based CPLDs

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Abstract

In this paper, we proposed a new technology mapping algorithm for CPLD under the time constraint (TMCPLD-II). In our technology mapping algorithm, we generate the feasible clusters from a given Boolean. The generated feasible clusters create clusters with minimum area under the time constraint. A covered Boolean network is transformed to a Boolean equation. The transformed equations are reconstructed in order to fit to an architecture of selected target CPLD by using collapsing and bin-packing. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the existing algorithms. The experimental results show that our approach is better than any of the existing algorithms in the number of logic blocks.