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DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
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DAC '94 Proceedings of the 31st annual Design Automation Conference
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DAC '98 Proceedings of the 35th annual Design Automation Conference
Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks
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Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Functional Decomposition with Application to FPGA Synthesis
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Synthesis and Optimization of Digital Circuits
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The paper presents one concept of decomposition methods dedicated to PAL-based CPLDs. The proposed approach is an alternative to the classical one, which is based on two-level minimization of separate single-output functions. The key idea of the algorithm is to search for free blocks that could be implemented in PAL-based logic blocks containing a limited number of product terms. In order to better exploit the number of product terms, two-stage decomposition and BDD-based decomposition are to be used. In BDD-based decomposition methods, functions are represented by Reduced Ordered Binary Decision Diagrams (ROBDDs). The results of experiments prove that the proposed solution is more effective, in terms of the usage of programmable device resources, compared with the classical ones.