Functional multiple-output decomposition: theory and an implicit algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Technology mapping for large complex PLDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hybrid product term and LUT based architectures using embedded memory blocks
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Synthesis for FPGAs with embedded memory blocks
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
The Hybrid Field-Programmable Architecture
IEEE Design & Test
Implicit computation of compatible sets for state minimization of ISFSMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic synthesis based on decomposition for CPLDs
Microprocessors & Microsystems
Decomposition-based logic synthesis for PAL-based CPLDs
International Journal of Applied Mathematics and Computer Science
| Hi-index | 0.00 |
In some modern FPGAs and CPLDs, PLA(programmable logic array)-style logic blocks can be used as the storage elements for improved logic density and performance. PLA-style logic blocks were originally deployed in the early PLDs. Due to recent research developments in the FPGA community such as [6] and [4], PLA-style logic blocks are becoming an effective storage alternative in FPGAs. This paper presents an approach with clustering and functional decomposition to implement the circuits using the minimum number of PLA-style logic blocks. One important feature is that it simultaneously considers the routing resource reduction for better circuit performance after place-and-route. In order to effectively use PLA-style logic blocks in large clusters, functional decompositions are used to decompose large clusters so that the encoding functions and base functions can be mapped into PLA-blocks. Furthermore, implicit representation[5] of the crucial steps in the functional decomposition is used to consider 1) number of inputs, 2) number of product terms. 3) number of outputs required for the PLA-block synthesis. We have developed an algorithm called PLA_SynT that can be used in the logic synthesis flow for CPLDs and FPGAs with PLA-blocks. MCNC benchmarks are used to test PLA_SynT and the experimental results are compared with TEMPLA[1]. PLA_SynT shows 10.24% improvement over TEMPLA[1], in terms of the number of PLA-blocks needed to implement the circuit. PLA_SynT also shows 14.41% improvement over EMB_Syn[3] in circuit performances while maintaining comparable circuit areas.