Architecture of centralized field-configurable memory
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Hybrid product term and LUT based architectures using embedded memory blocks
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Routing Architectures for Hierarchical Field Programmable Gate Arrays
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
The Design of a New FPGA Architecture
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Technology mapping issues for an FPGA with lookup tables and PLA-like blocks
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Area-Optimized Technology Mapping for Hybrid FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Product-term-based synthesizable embedded programmable logic cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
This paper proposes a new field-programmable architecture that is a combination of two existing technologies: Field- Programmable Gate Arrays (FPGAs) based on LookUp Tables (LUTs), and Complex Programmable Logic Devices based on PLA-like blocks. The methodology used for development of the new architecture, called Hybrid FPGA, is based on analysis of a large set of benchmark circuits, in which we determine what types of logic resources best match the needs of the circuits. The proposed Hybrid FPGA is evaluated by technology mapping a set of circuits into the new architecture and estimating the total chip area needed and the depth for each circuit, compared to the area and depth that would be required if only LUTs were available. Our results indicate that on average LUT-based FPGAs need 78% more area than the Hybrid, while providing roughly the same depth for the circuits. Also, we show that it is possible to optimize the circuits for depth, such that the critical path of the circuits implemented in the new architecture is significantly shorter than the critical path when they are mapped to LUT-based FPGAs.