Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Memory-to-memory connection structures in FPGAs with embedded memory arrays
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Memory interfacing and instruction specification for reconfigurable processors
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA Architectural Research: A Survey
IEEE Design & Test
The Hybrid Field-Programmable Architecture
IEEE Design & Test
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
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As the capacities of FPGAs grow, it becomes feasible to implement the memory portions of systems directly on an FPGA together with logic. We believe that such an FPGA must contain specialized architectural support in order to implement memories efficiently. The key feature of such architectural support is that it must be flexible enough to accommodate many different memory shapes (widths and depths) as well as allowing different numbers of independently-addressed memory blocks. This paper describes a family of centralized Field-Configurable Memory architectures which consist of a number of memory arrays and dedicated mapping blocks to combine these arrays. We also present a method for comparing these architectures, and use this method to examine the tradeoffs involved in choosing the array size and mapping block capabilities.