Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Architecture of centralized field-configurable memory
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
Routing Architectures for Hierarchical Field Programmable Gate Arrays
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
High speed c-means clustering in reconfigurable hardware
Microprocessors & Microsystems
| Hi-index | 0.00 |
A recent article by S. Brown and J. Rose (see ibid., vol.13, no.2, p.42-57, 1996) summarized the classes of field programmable devices currently available and described many of the most important commercial devices. We describe current research studies, evaluating the enhancements to FPGA architecture each recommends and how these architectures affect the two most important metrics: total chip area and speed performance. We also note examples of commercial products possessing features consistent with the recommendations of the research studies