Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Directional bias and non-uniformity in FPGA global routing architectures
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
FPGA Architectural Research: A Survey
IEEE Design & Test
Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
BIST-Based Diagnosis of FPGA Interconnect
ITC '02 Proceedings of the 2002 IEEE International Test Conference
The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Proceedings of the conference on Design, automation and test in Europe - Volume 1
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
IEEE Design & Test
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Heavy Ion Effects on Configuration Logic of Virtex FPGAs
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
SEU mitigation for sram-based fpgas through dynamic partial reconfiguration
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Single-event-upset (SEU) awareness in FPGA routing
Proceedings of the 44th annual Design Automation Conference
A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices
Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies
Proceedings of the conference on Design, automation and test in Europe
Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
SEU-aware resource binding for modular redundancy based designs on FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
A study of the single event effects impact on functional mapping within flash-based FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Mitigation of soft errors in SRAM-based FPGAs using CAD tools
Computers and Electrical Engineering
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Scrubbing unit repositioning for fast error repair in FPGAs
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Hi-index | 14.98 |
The very high integration levels reached by VLSI technologies for SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs' configuration memory. Since the configuration memory defines which circuit an SRAM-based FPGA implements, any modification induced by SEUs may dramatically change the implemented circuit. When such devices are used in safety-critical applications, fault-tolerant techniques are needed to mitigate the effects of SEUs in FPGAs' configuration memory. In this paper, we analyze the effects induced by the SEUs in the configuration memory of SRAM-based FPGAs. The reported analysis outlines that SEUs in the FPGA's configuration memory are particularly critical since they are able to escape well-known fault masking techniques such as Triple Modular Redundancy (TMR). We then present a reliability-oriented place and route algorithm that, coupled with TMR, is able to effectively mitigate the effects of the considered faults. The effectiveness of the new reliability-oriented place and route algorithm is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique.