Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Embedded Robustness IPs for Transient-Error-Free ICs
IEEE Design & Test
Permanent Fault Repair for FPGAs with Limited Redundant Area
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Soft error rate estimation and mitigation for SRAM-based FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Going beyond TMR for protection against multiple faults
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
IEEE Transactions on Computers
SEU mitigation for sram-based fpgas through dynamic partial reconfiguration
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Dependable design technique for system-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Design of a soft-error robust microprocessor
Microelectronics Journal
Maximizing area-constrained partial fault tolerance in reconfigurable logic
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Hardware/software optimization of error detection implementation for real-time embedded systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes
Microelectronics Journal
Performance optimization of error detection based on speculative reconfiguration
Proceedings of the 48th Design Automation Conference
Fault tolerant system design and SEU injection based testing
Microprocessors & Microsystems
Microprocessors & Microsystems
| Hi-index | 0.00 |
This paper discusses high level techniques for designing fault tolerant systems in SRAM-based FPGAs, without modification in the FPGA architecture. Triple Modular Redundancy (TMR) has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The new technique proposed in this paper was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. We present some fault coverage results and a comparison with the TMR approach.