ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fault-tolerant computer system design
Fault-tolerant computer system design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
BOOM: a heuristic boolean minimizer
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Self-Checking Design in Eastern Europe
IEEE Design & Test
Fault Analysis for Networks with Concurrent Error Detection
IEEE Design & Test
Permanent Fault Repair for FPGAs with Limited Redundant Area
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Designing Self-Checking FPGAs through Error Detection Codes
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Concurrent Fault Detection in Random Combinational Logic
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Automatic Insertion of Fault-Tolerant Structures at the RT Level
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Integrated Design Approach for Self-Checking FPGAs
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
FPGA Based Design of the Railway's Interlocking Equipments
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
IEEE Design & Test
A design flow for protecting FPGA-based systems against single event upsets
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Soft core based embedded systems in critical aerospace applications
Journal of Systems Architecture: the EUROMICRO Journal
The influence of implementation type on dependability parameters
Microprocessors & Microsystems
Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms
Journal of Electronic Testing: Theory and Applications
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A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters.