A note on strongly fault-secure sequential circuits
IEEE Transactions on Computers
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Probability to Achieve TSC Goal
IEEE Transactions on Computers
A New Design Method for Self-Checking Unidirectional Combinational Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
On TSC Checkers for m-out-of-n Codes
IEEE Transactions on Computers
Designing Networks with Error Detection Properties through the Fault-Error Relation
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Self-checking FSMs based on a constant distance state encoding
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Redundant Faults in TSC Networks: Definition and Removal
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
A TSC evaluation function for combinational circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Dependable design technique for system-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
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Hardware and information redundancy are two among the most widespread strategies for designing circuits with concurrent detection properties. These design approaches guarantee the desired property by partitioning the set of output configurations that a device may produce into two classes: those produced in a fault free situation and those caused by at least a fault within either the network or the checker circuit. This functional property allows the coverage of all faults that produce an error on the outputs such that the generated configuration does not belong to the fault-free output set. Whenever this does not happen, the fault is not detected, either causing no error (fault redundant with respect to the input configuration) or producing a fault-free output different from the correct one (critical situation). To achieve a complete fault coverage a constrained synthesis must support the functional encoding, guaranteeing that each fault produces only detectable errors. If there is a lack, either at functional encoding level or at the structural synthesis level, due to costs and complexity, the device will only be partially self-checking.This paper proposes an approach, supported by a tool the authors developed, for fault analysis and simulation of networks designed to have concurrent detection properties, either partially or completely, to characterize all faults that may affect the device, determining the coverage, when incomplete, extracting test vectors and other parameters for evaluating the quality of the device. The methodology may be used both during the realization of the device, supporting network realization to fulfill the functional encoding, and a-posteriori, when the device is partially o totally self-checking, for an evaluation and possible comparison with different solutions.