Designing Networks with Error Detection Properties through the Fault-Error Relation

  • Authors:
  • Cristiana Bolchini;Donatella Sciuto;Fabio Salice

  • Affiliations:
  • -;-;-

  • Venue:
  • DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
  • Year:
  • 1997

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Abstract

The paper proposes an approach for designing TSC networks by means of error detecting code application, based on the analysis of the desired fault-error relation. The network structure is analyzed by taking into account each possible fault, belonging to the adopted fault set, and by verifying if the produced error is detectable with respect to the adopted encoding. If undetectable faults are located, the network is locally modified, so that area overheads for TSC designs is limited.