Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Self-checking combinational circuit design for single and unidirectional multibit error
Journal of Electronic Testing: Theory and Applications
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fail-Safe Interfaces for VLSI: Theoretical Foundations and Implementation
IEEE Transactions on Computers
Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
IC Defects-Based Testability Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Synthesis of Multi-level Self-Checking Logic
Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Designing Networks with Error Detection Properties through the Fault-Error Relation
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Novel Methodology for Designing TSC Networks Based on the Parity Bit Code
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Self-dual parity checking-A new method for on-line testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |