Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection

Authors:
Nur A. Touba;Edward J. McCluskey
Affiliations:
Center for Reliable Computing, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA;Center for Reliable Computing, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA
Venue:
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Year:
1994

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Abstract

This paper presents new logic synthesis techniques for generating multilevel circuits with concurrent error detection based on a parity-check code scheme that can detect all errors caused by single stuck-at faults. These synthesis techniques fully automate the design process and allow for a better quality result than previous methods thereby reducing the cost of concurrent error detection. An algorithm is described for selecting a good parity-check code for encoding the outputs of a circuit. Once the code has been chosen, a new procedure called structure-constrained logic optimization is used to minimize the area of the circuit as much as possible while still using a circuit structure that ensures that single stuck-at faults cannot produce undetected errors. The implementation that is generated is path fault secure and when augmented by a checker forms a self-checking circuit. Results indicate that self-checking multilevel circuits can be generated which require significantly less area than using duplication.