ESP: a new standard cell placement package using simulated evolution
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Performance of a parallel algorithm for standard cell placement on the Intel hypercube
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Query optimization by simulated annealing
SIGMOD '87 Proceedings of the 1987 ACM SIGMOD international conference on Management of data
Enhanced simulated annealing for automatic reconfiguration of multiprocessors in space
IEA/AIE '89 Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1
Efficient final placement based on nets-as-points
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A parallel row-based algorithm for standard cell placement with integrated error control
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
On a parallel partitioning technique for use with conservative parallel simulation
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
A static partitioning and mapping algorithm for conservative parallel simulations
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A performance-driven IC/MCM placement algorithm featuring explicit design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A combined hierarchical placement algorithm
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance driven global routing for standard cell design
Proceedings of the 1997 international symposium on Physical design
IEEE Transactions on Computers
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Clustering based simulated annealing for standard cell placement
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Proud: a fast sea-of-gates placement algorithm
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Greedy, Prohibition, and Reactive Heuristics for Graph Partitioning
IEEE Transactions on Computers
Relaxation and clustering in a local search framework: application to linear placement
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Highlight of VLSI at research Berkeley
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Copyright protection of designs based on multi source IPs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
Congestion estimation during top-down placement
Proceedings of the 2001 international symposium on Physical design
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations
Journal of Heuristics
Genetic Algorithm and Graph Partitioning
IEEE Transactions on Computers
Parallel Simulated Annealing Algorithms for Cell Placement on Hypercube Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Fuzzy simulated evolution algorithm for VLSI cell placement
Computers and Industrial Engineering - Special issue: Focussed issue on applied meta-heuristics
Clock-Skew Constrained Cell Placement
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region
EURO-DAC '90 Proceedings of the conference on European design automation
Proceedings of the 2004 international symposium on Physical design
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
RQL: global placement via relaxed quadratic spreading and linearization
Proceedings of the 44th annual Design Automation Conference
Parallel multi-level analytical global placement on graphics processing units
Proceedings of the 2009 International Conference on Computer-Aided Design
A SVD-based fragile watermarking scheme for image authentication
IWDW'02 Proceedings of the 1st international conference on Digital watermarking
WRIP: logic restructuring techniques for wirelength-driven incremental placement
Proceedings of the great lakes symposium on VLSI
Composite stock cutting through simulated annealing
Mathematical and Computer Modelling: An International Journal
From design to design automation
Proceedings of the 2014 on International symposium on physical design
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TimberWolf3.2 is a new standard cell placement and global routing package. The placement and global routing proceed over 3 distinct stages. The general combinatorial optimization technique known as simulated annealing is used during the first two stages of the placement. In the first stage, TimberWolf3.2 places the cells such that the total estimated interconnect cost is minimized. During the second stage, TimberWolf3.2 inserts feed through cells as required and the minimization of the total estimated interconnect cost proceeds again in the manner of simulated annealing. The second stage comes to a close following a global routing step, in which the number of wiring tracks needed is accurately estimated. During the third and final stage, local changes are made to the placement whenever such changes result in a reduction in the number of wiring tracks required. TimberWolf3.2 has achieved area savings ranging from 15 to 75% in experiments on numerous industrial circuits.