Delay and area optimization in standard-cell design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ALPS2: a standard cell layout system for double-layer metal technology
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
PLINT layout system for VLSI chips
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
Futures for partitioning in physical design (tutorial)
ISPD '98 Proceedings of the 1998 international symposium on Physical design
IEEE Transactions on Computers
Potential-NRG: placement with incomplete data
DAC '98 Proceedings of the 35th annual Design Automation Conference
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Multi-center congestion estimation and minimization during placement
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Modeling and minimization of routing congestion
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
Reporting of standard cell placement results
Proceedings of the 2001 international symposium on Physical design
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Almost optimum placement legalization by minimum cost flow and dynamic programming
Proceedings of the 2004 international symposium on Physical design
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
Evaluation of Placement Techniques for DNA Probe Array Layout
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A path-based timing-driven quadratic placement algorithm
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
An improved algorithm for sequence pair generation
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I
Multi-stage detailed placement algorithm for large-scale mixed-mode layout design
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part IV
A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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We present a new approach to the placement problem. The proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular input. After determination of the grid size, the placement is carried out in three steps: global placement, detailed placement and final optimization. We will show that the output of the global placement can also serve as a fast and accurate predictor. Current implementation is based on simulated annealing. We have put all algorithms together in a placement package called NRG (pronounced N-er-G). In addition to area minimization, NRG can perform timing-driven placement. Experimental results are strong. We improve TimberWolf's results (version 1.2, the commercial version which is suppose to be better than all university versions including version 7) by about 5%. Our predictor can estimate the wirelength within 10-20% accuracy offering 2-20x speedup compared with the actual placement algorithm.