Min-Cut Partitioning on Underlying Tree and Graph Structures
IEEE Transactions on Computers
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Performance driven floorplanning for FPGA based designs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search
IEEE Transactions on Parallel and Distributed Systems
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Maximum independent sets on transitive graphs and their applications in testing and CAD
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Nostradamus: a floorplanner of uncertain design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Device-level early floorplanning algorithms for RF circuits
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multi-center congestion estimation and minimization during placement
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Analytical approach to custom datapath design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Single step current driven routing of multiterminal signal nets for analog applications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Slicible rectangular graphs and their optimal floorplans
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Fishbone: a block-level placement and routing scheme
Proceedings of the 2003 international symposium on Physical design
A Partitioning Programming Environment for a Novel Parallel Architecture
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Multipartite Tables in JBits for the Evaluation of Functions on FPGAs
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
JRoute: A Run-Time Routing API for FPGA Hardware
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Physical Design of CMOS Chips in Six Easy Steps
SOFSEM '00 Proceedings of the 27th Conference on Current Trends in Theory and Practice of Informatics
Integrated Iterative Approach to FPGA Placement
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Heuristic cell partitioning scheme based on min-cut scheme in cellular networks
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
Geometric bipartitioning problem and its applications to VLSI
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Channel routing in Manhattan-diagonal model
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Implementing a genetic algorithm on a parallel custom computing machine
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Efficient placement and routing in grid-based networks
Proceedings of the 2005 ACM symposium on Applied computing
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Hierarchical partitioning of VLSI floorplans by staircases
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Floorplanning-Synthesis Methodology For Multiple Chip Module Design
Journal of Integrated Design & Process Science
Local properties of geometric graphs
Computational Geometry: Theory and Applications
A Cost-Optimal Algorithm for Guard Zone Problem
ICDCN '09 Proceedings of the 10th International Conference on Distributed Computing and Networking
Implementing and clustering modules with complex delays
Integration, the VLSI Journal
Scenario-oriented design for single-chip heterogeneous multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routability checking for three-dimensional architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A maze routing algorithm based on two dimensional cellular automata
ACRI'06 Proceedings of the 7th international conference on Cellular Automata for Research and Industry
A faster hierarchical balanced bipartitioner for VLSI floorplans using monotone staircase cuts
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Parameterized Domination in Circle Graphs
Theory of Computing Systems
Hi-index | 0.00 |
From the Publisher:This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.